STM32L443xx HAL User Manual
Defines
Calculate frequencies
RCC Exported Macros

Defines

#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)
 Helper macro to calculate the PLLCLK frequency on system domain.
#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
 Helper macro to calculate the PLLCLK frequency used on SAI domain.
#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
 Helper macro to calculate the PLLCLK frequency used on 48M domain.
#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__)
 Helper macro to calculate the PLLSAI1 frequency used for SAI domain.
#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__)
 Helper macro to calculate the PLLSAI1 frequency used on 48M domain.
#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__)
 Helper macro to calculate the PLLSAI1 frequency used on ADC domain.
#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__)
 Helper macro to calculate the PLLSAI2 frequency used for SAI domain.
#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__)   ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
 Helper macro to calculate the HCLK frequency.
#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__)   ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
 Helper macro to calculate the PCLK1 frequency (ABP1)
#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__)   ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
 Helper macro to calculate the PCLK2 frequency (ABP2)
#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__)
 Helper macro to calculate the MSI frequency (in Hz)

Define Documentation

#define __LL_RCC_CALC_HCLK_FREQ (   __SYSCLKFREQ__,
  __AHBPRESCALER__ 
)    ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])

Helper macro to calculate the HCLK frequency.

Parameters:
__SYSCLKFREQ__SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
__AHBPRESCALER__This parameter can be one of the following values:
Return values:
HCLKclock frequency (in Hz)

Definition at line 1938 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

#define __LL_RCC_CALC_MSI_FREQ (   __MSISEL__,
  __MSIRANGE__ 
)
Value:
(((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
                           (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
                           (MSIRangeTable[(__MSIRANGE__) >> 4U]))

Helper macro to calculate the MSI frequency (in Hz)

Note:
__MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY, __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby() else by LL_RCC_MSI_GetRange() ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), (LL_RCC_MSI_IsEnabledRangeSelect()? LL_RCC_MSI_GetRange(): LL_RCC_MSI_GetRangeAfterStandby()))
Parameters:
__MSISEL__This parameter can be one of the following values:
__MSIRANGE__This parameter can be one of the following values:
Return values:
MSIclock frequency (in Hz)

Definition at line 1998 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetUSBClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), and RCC_PLLSAI1_GetFreqDomain_SAI().

#define __LL_RCC_CALC_PCLK1_FREQ (   __HCLKFREQ__,
  __APB1PRESCALER__ 
)    ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])

Helper macro to calculate the PCLK1 frequency (ABP1)

Parameters:
__HCLKFREQ__HCLK frequency
__APB1PRESCALER__This parameter can be one of the following values:
Return values:
PCLK1clock frequency (in Hz)

Definition at line 1951 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

#define __LL_RCC_CALC_PCLK2_FREQ (   __HCLKFREQ__,
  __APB2PRESCALER__ 
)    ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])

Helper macro to calculate the PCLK2 frequency (ABP2)

Parameters:
__HCLKFREQ__HCLK frequency
__APB2PRESCALER__This parameter can be one of the following values:
Return values:
PCLK2clock frequency (in Hz)

Definition at line 1964 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

#define __LL_RCC_CALC_PLLCLK_48M_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLN__,
  __PLLQ__ 
)
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
                   ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))

Helper macro to calculate the PLLCLK frequency used on 48M domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetQ ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__This parameter can be one of the following values: (*) value not defined in all devices.
__PLLN__Between 8 and 86 or 127 depending on devices
__PLLQ__This parameter can be one of the following values:
Return values:
PLLclock frequency (in Hz)

Definition at line 1402 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M().

#define __LL_RCC_CALC_PLLCLK_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLN__,
  __PLLR__ 
)
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
                   ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))

Helper macro to calculate the PLLCLK frequency on system domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetR ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__This parameter can be one of the following values: (*) value not defined in all devices.
__PLLN__Between 8 and 86 or 127 depending on devices
__PLLR__This parameter can be one of the following values:
Return values:
PLLclock frequency (in Hz)

Definition at line 1277 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

#define __LL_RCC_CALC_PLLCLK_SAI_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLN__,
  __PLLP__ 
)
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
                   ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))

Helper macro to calculate the PLLCLK frequency used on SAI domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetP ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__This parameter can be one of the following values: (*) value not defined in all devices.
__PLLN__Between 8 and 86 or 127 depending on devices
__PLLP__This parameter can be one of the following values:
Return values:
PLLclock frequency (in Hz)

Definition at line 1340 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SAI().

#define __LL_RCC_CALC_PLLSAI1_48M_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLSAI1N__,
  __PLLSAI1Q__ 
)
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
                    ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))

Helper macro to calculate the PLLSAI1 frequency used on 48M domain.

Note:
ex: __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI1_GetN (), LL_RCC_PLLSAI1_GetQ ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__This parameter can be one of the following values:
__PLLSAI1N__Between 8 and 86
__PLLSAI1Q__This parameter can be one of the following values:
Return values:
PLLSAI1clock frequency (in Hz)

Definition at line 1605 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_48M().

#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLSAI1N__,
  __PLLSAI1R__ 
)
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
                    ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))

Helper macro to calculate the PLLSAI1 frequency used on ADC domain.

Note:
ex: __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI1_GetN (), LL_RCC_PLLSAI1_GetR ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__This parameter can be one of the following values:
__PLLSAI1N__Between 8 and 86
__PLLSAI1R__This parameter can be one of the following values:
Return values:
PLLSAI1clock frequency (in Hz)

Definition at line 1669 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_ADC().

#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLSAI1N__,
  __PLLSAI1P__ 
)
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
                    ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))

Helper macro to calculate the PLLSAI1 frequency used for SAI domain.

Note:
ex: __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI1_GetN (), LL_RCC_PLLSAI1_GetP ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__This parameter can be one of the following values:
__PLLSAI1N__Between 8 and 86 or 127 depending on devices
__PLLSAI1P__This parameter can be one of the following values:
Return values:
PLLSAI1clock frequency (in Hz)

Definition at line 1516 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_SAI().

#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLSAI2N__,
  __PLLSAI2P__ 
)
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
                    (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))

Helper macro to calculate the PLLSAI2 frequency used for SAI domain.

Note:
ex: __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI2_GetN (), LL_RCC_PLLSAI2_GetP ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__This parameter can be one of the following values:
__PLLSAI2N__Between 8 and 86
__PLLSAI2P__This parameter can be one of the following values:
  • LL_RCC_PLLSAI2P_DIV_7
  • LL_RCC_PLLSAI2P_DIV_17
Return values:
PLLSAI2clock frequency (in Hz)

Definition at line 1811 of file stm32l4xx_ll_rcc.h.

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