STM32L443xx HAL User Manual: stm32l4xx_ll

Header file of RCC LL module. More...

#include "stm32l4xx.h"

Data Structures
struct	LL_RCC_ClocksTypeDef
	RCC Clocks Frequency Structure. More...
Defines
#define	RCC_OFFSET_CCIPR 0U
#define	RCC_OFFSET_CCIPR2 0x14U
#define	LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC
#define	LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
#define	LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC
#define	LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
#define	LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
#define	LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
#define	LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC
#define	LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC
#define	LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
#define	LL_RCC_CICR_CSSC RCC_CICR_CSSC
#define	LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF
#define	LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
#define	LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF
#define	LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
#define	LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
#define	LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
#define	LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF
#define	LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF
#define	LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
#define	LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
#define	LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF
#define	LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define	LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define	LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define	LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define	LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define	LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define	LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF
#define	LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE
#define	LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
#define	LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE
#define	LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
#define	LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
#define	LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
#define	LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE
#define	LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE
#define	LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE
#define	LL_RCC_LSEDRIVE_LOW 0x00000000U
#define	LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define	LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define	LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define	LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0
#define	LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1
#define	LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2
#define	LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3
#define	LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4
#define	LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5
#define	LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6
#define	LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7
#define	LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8
#define	LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9
#define	LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10
#define	LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11
#define	LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1
#define	LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2
#define	LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4
#define	LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8
#define	LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U
#define	LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL
#define	LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI
#define	LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define	LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define	LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL
#define	LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI
#define	LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define	LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define	LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL
#define	LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
#define	LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
#define	LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
#define	LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
#define	LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
#define	LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
#define	LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
#define	LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
#define	LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512
#define	LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
#define	LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
#define	LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
#define	LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
#define	LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16
#define	LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
#define	LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
#define	LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
#define	LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
#define	LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16
#define	LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U
#define	LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
#define	LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define	LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define	LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1
#define	LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1)
#define	LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define	LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2)
#define	LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2)
#define	LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2)
#define	LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3
#define	LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1
#define	LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2
#define	LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4
#define	LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8
#define	LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16
#define	LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define	LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
#define	LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U)
#define	LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_0)
#define	LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_1)
#define	LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL)
#define	LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U)
#define	LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_0)
#define	LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_1)
#define	LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL)
#define	LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U)
#define	LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL_0)
#define	LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL_1)
#define	LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL)
#define	LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U
#define	LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define	LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define	LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL
#define	LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U))
#define	LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos))
#define	LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos))
#define	LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U))
#define	LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos))
#define	LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos))
#define	LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U))
#define	LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos))
#define	LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos))
#define	LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL
#define	LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_0 >> 16U))
#define	LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_1 >> 16U))
#define	LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL >> 16U))
#define	LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL
#define	LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_0 >> 16U))
#define	LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_1 >> 16U))
#define	LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL >> 16U))
#define	LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL
#define	LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_1 >> 16U))
#define	LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL >> 16U))
#define	LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U
#define	LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define	LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define	LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define	LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U
#define	LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define	LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define	LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define	LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U
#define	LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define	LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define	LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define	LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U
#define	LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
#define	LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
#define	LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U
#define	LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
#define	LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL
#define	LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL
#define	LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL
#define	LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL
#define	LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos))
#define	LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos))
#define	LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos))
#define	LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL
#define	LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL
#define	LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL
#define	LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL
#define	LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL
#define	LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL
#define	LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL
#define	LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL
#define	LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define	LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define	LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define	LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
#define	LL_RCC_PLLSOURCE_NONE 0x00000000U
#define	LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI
#define	LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define	LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
#define	LL_RCC_PLLM_DIV_1 0x00000000U
#define	LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)
#define	LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)
#define	LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0)
#define	LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)
#define	LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0)
#define	LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1)
#define	LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0)
#define	LL_RCC_PLLR_DIV_2 0x00000000U
#define	LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0)
#define	LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1)
#define	LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)
#define	LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1)
#define	LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2)
#define	LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1)
#define	LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3)
#define	LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1)
#define	LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2)
#define	LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1)
#define	LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4)
#define	LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_1)
#define	LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2)
#define	LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1)
#define	LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3)
#define	LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1)
#define	LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2)
#define	LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1)
#define	LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0)
#define	LL_RCC_PLLQ_DIV_2 0x00000000U
#define	LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0)
#define	LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1)
#define	LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)
#define	LL_RCC_PLLSAI1Q_DIV_2 0x00000000U
#define	LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0)
#define	LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1)
#define	LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q)
#define	LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
#define	LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)
#define	LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
#define	LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)
#define	LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
#define	LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)
#define	LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
#define	LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)
#define	LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
#define	LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)
#define	LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
#define	LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)
#define	LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
#define	LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)
#define	LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
#define	LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
#define	LL_RCC_PLLSAI1R_DIV_2 0x00000000U
#define	LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0)
#define	LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1)
#define	LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R)
#define	LL_RCC_MSIRANGESEL_STANDBY 0U
#define	LL_RCC_MSIRANGESEL_RUN 1U
#define	LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
	Write a value in RCC register.
#define	LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
	Read a value in RCC register.
#define	__LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)
	Helper macro to calculate the PLLCLK frequency on system domain.
#define	__LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
	Helper macro to calculate the PLLCLK frequency used on SAI domain.
#define	__LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
	Helper macro to calculate the PLLCLK frequency used on 48M domain.
#define	__LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__)
	Helper macro to calculate the PLLSAI1 frequency used for SAI domain.
#define	__LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__)
	Helper macro to calculate the PLLSAI1 frequency used on 48M domain.
#define	__LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__)
	Helper macro to calculate the PLLSAI1 frequency used on ADC domain.
#define	__LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__)
	Helper macro to calculate the PLLSAI2 frequency used for SAI domain.
#define	__LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
	Helper macro to calculate the HCLK frequency.
#define	__LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
	Helper macro to calculate the PCLK1 frequency (ABP1)
#define	__LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
	Helper macro to calculate the PCLK2 frequency (ABP2)
#define	__LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__)
	Helper macro to calculate the MSI frequency (in Hz)
Functions
__STATIC_INLINE void	LL_RCC_HSE_EnableCSS (void)
	Enable the Clock Security System.
__STATIC_INLINE void	LL_RCC_HSE_EnableBypass (void)
	Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void	LL_RCC_HSE_DisableBypass (void)
	Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void	LL_RCC_HSE_Enable (void)
	Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void	LL_RCC_HSE_Disable (void)
	Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t	LL_RCC_HSE_IsReady (void)
	Check if HSE oscillator Ready.
__STATIC_INLINE void	LL_RCC_HSI_EnableInStopMode (void)
	Enable HSI even in stop mode.
__STATIC_INLINE void	LL_RCC_HSI_DisableInStopMode (void)
	Disable HSI in stop mode.
__STATIC_INLINE uint32_t	LL_RCC_HSI_IsEnabledInStopMode (void)
	Check if HSI is enabled in stop mode.
__STATIC_INLINE void	LL_RCC_HSI_Enable (void)
	Enable HSI oscillator.
__STATIC_INLINE void	LL_RCC_HSI_Disable (void)
	Disable HSI oscillator.
__STATIC_INLINE uint32_t	LL_RCC_HSI_IsReady (void)
	Check if HSI clock is ready.
__STATIC_INLINE void	LL_RCC_HSI_EnableAutoFromStop (void)
	Enable HSI Automatic from stop mode.
__STATIC_INLINE void	LL_RCC_HSI_DisableAutoFromStop (void)
	Disable HSI Automatic from stop mode.
__STATIC_INLINE uint32_t	LL_RCC_HSI_GetCalibration (void)
	Get HSI Calibration value.
__STATIC_INLINE void	LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
	Set HSI Calibration trimming.
__STATIC_INLINE uint32_t	LL_RCC_HSI_GetCalibTrimming (void)
	Get HSI Calibration trimming.
__STATIC_INLINE void	LL_RCC_HSI48_Enable (void)
	Enable HSI48.
__STATIC_INLINE void	LL_RCC_HSI48_Disable (void)
	Disable HSI48.
__STATIC_INLINE uint32_t	LL_RCC_HSI48_IsReady (void)
	Check if HSI48 oscillator Ready.
__STATIC_INLINE uint32_t	LL_RCC_HSI48_GetCalibration (void)
	Get HSI48 Calibration value.
__STATIC_INLINE void	LL_RCC_LSE_Enable (void)
	Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void	LL_RCC_LSE_Disable (void)
	Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void	LL_RCC_LSE_EnableBypass (void)
	Enable external clock source (LSE bypass).
__STATIC_INLINE void	LL_RCC_LSE_DisableBypass (void)
	Disable external clock source (LSE bypass).
__STATIC_INLINE void	LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
	Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t	LL_RCC_LSE_GetDriveCapability (void)
	Get LSE oscillator drive capability.
__STATIC_INLINE void	LL_RCC_LSE_EnableCSS (void)
	Enable Clock security system on LSE.
__STATIC_INLINE void	LL_RCC_LSE_DisableCSS (void)
	Disable Clock security system on LSE.
__STATIC_INLINE uint32_t	LL_RCC_LSE_IsReady (void)
	Check if LSE oscillator Ready.
__STATIC_INLINE uint32_t	LL_RCC_LSE_IsCSSDetected (void)
	Check if CSS on LSE failure Detection.
__STATIC_INLINE void	LL_RCC_LSI_Enable (void)
	Enable LSI Oscillator.
__STATIC_INLINE void	LL_RCC_LSI_Disable (void)
	Disable LSI Oscillator.
__STATIC_INLINE uint32_t	LL_RCC_LSI_IsReady (void)
	Check if LSI is Ready.
__STATIC_INLINE void	LL_RCC_MSI_Enable (void)
	Enable MSI oscillator.
__STATIC_INLINE void	LL_RCC_MSI_Disable (void)
	Disable MSI oscillator.
__STATIC_INLINE uint32_t	LL_RCC_MSI_IsReady (void)
	Check if MSI oscillator Ready.
__STATIC_INLINE void	LL_RCC_MSI_EnablePLLMode (void)
	Enable MSI PLL-mode (Hardware auto calibration with LSE)
__STATIC_INLINE void	LL_RCC_MSI_DisablePLLMode (void)
	Disable MSI-PLL mode.
__STATIC_INLINE void	LL_RCC_MSI_EnableRangeSelection (void)
	Enable MSI clock range selection with MSIRANGE register.
__STATIC_INLINE uint32_t	LL_RCC_MSI_IsEnabledRangeSelect (void)
	Check if MSI clock range is selected with MSIRANGE register.
__STATIC_INLINE void	LL_RCC_MSI_SetRange (uint32_t Range)
	Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
__STATIC_INLINE uint32_t	LL_RCC_MSI_GetRange (void)
	Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
__STATIC_INLINE void	LL_RCC_MSI_SetRangeAfterStandby (uint32_t Range)
	Configure MSI range used after standby.
__STATIC_INLINE uint32_t	LL_RCC_MSI_GetRangeAfterStandby (void)
	Get MSI range used after standby.
__STATIC_INLINE uint32_t	LL_RCC_MSI_GetCalibration (void)
	Get MSI Calibration value.
__STATIC_INLINE void	LL_RCC_MSI_SetCalibTrimming (uint32_t Value)
	Set MSI Calibration trimming.
__STATIC_INLINE uint32_t	LL_RCC_MSI_GetCalibTrimming (void)
	Get MSI Calibration trimming.
__STATIC_INLINE void	LL_RCC_LSCO_Enable (void)
	Enable Low speed clock.
__STATIC_INLINE void	LL_RCC_LSCO_Disable (void)
	Disable Low speed clock.
__STATIC_INLINE void	LL_RCC_LSCO_SetSource (uint32_t Source)
	Configure Low speed clock selection.
__STATIC_INLINE uint32_t	LL_RCC_LSCO_GetSource (void)
	Get Low speed clock selection.
__STATIC_INLINE void	LL_RCC_SetSysClkSource (uint32_t Source)
	Configure the system clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetSysClkSource (void)
	Get the system clock source.
__STATIC_INLINE void	LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
	Set AHB prescaler.
__STATIC_INLINE void	LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
	Set APB1 prescaler.
__STATIC_INLINE void	LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
	Set APB2 prescaler.
__STATIC_INLINE uint32_t	LL_RCC_GetAHBPrescaler (void)
	Get AHB prescaler.
__STATIC_INLINE uint32_t	LL_RCC_GetAPB1Prescaler (void)
	Get APB1 prescaler.
__STATIC_INLINE uint32_t	LL_RCC_GetAPB2Prescaler (void)
	Get APB2 prescaler.
__STATIC_INLINE void	LL_RCC_SetClkAfterWakeFromStop (uint32_t Clock)
	Set Clock After Wake-Up From Stop mode.
__STATIC_INLINE uint32_t	LL_RCC_GetClkAfterWakeFromStop (void)
	Get Clock After Wake-Up From Stop mode.
__STATIC_INLINE void	LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
	Configure MCOx.
__STATIC_INLINE void	LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
	Configure USARTx clock source.
__STATIC_INLINE void	LL_RCC_SetLPUARTClockSource (uint32_t LPUARTxSource)
	Configure LPUART1x clock source.
__STATIC_INLINE void	LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
	Configure I2Cx clock source.
__STATIC_INLINE void	LL_RCC_SetLPTIMClockSource (uint32_t LPTIMxSource)
	Configure LPTIMx clock source.
__STATIC_INLINE void	LL_RCC_SetSAIClockSource (uint32_t SAIxSource)
	Configure SAIx clock source.
__STATIC_INLINE void	LL_RCC_SetSDMMCClockSource (uint32_t SDMMCxSource)
	Configure SDMMC1 clock source.
__STATIC_INLINE void	LL_RCC_SetRNGClockSource (uint32_t RNGxSource)
	Configure RNG clock source.
__STATIC_INLINE void	LL_RCC_SetUSBClockSource (uint32_t USBxSource)
	Configure USB clock source.
__STATIC_INLINE void	LL_RCC_SetADCClockSource (uint32_t ADCxSource)
	Configure ADC clock source.
__STATIC_INLINE void	LL_RCC_SetSWPMIClockSource (uint32_t SWPMIxSource)
	Configure SWPMI clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetUSARTClockSource (uint32_t USARTx)
	Get USARTx clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetLPUARTClockSource (uint32_t LPUARTx)
	Get LPUARTx clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetI2CClockSource (uint32_t I2Cx)
	Get I2Cx clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetLPTIMClockSource (uint32_t LPTIMx)
	Get LPTIMx clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetSAIClockSource (uint32_t SAIx)
	Get SAIx clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetSDMMCClockSource (uint32_t SDMMCx)
	Get SDMMCx clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetRNGClockSource (uint32_t RNGx)
	Get RNGx clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetUSBClockSource (uint32_t USBx)
	Get USBx clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetADCClockSource (uint32_t ADCx)
	Get ADCx clock source.
__STATIC_INLINE uint32_t	LL_RCC_GetSWPMIClockSource (uint32_t SPWMIx)
	Get SWPMIx clock source.
__STATIC_INLINE void	LL_RCC_SetRTCClockSource (uint32_t Source)
	Set RTC Clock Source.
__STATIC_INLINE uint32_t	LL_RCC_GetRTCClockSource (void)
	Get RTC Clock Source.
__STATIC_INLINE void	LL_RCC_EnableRTC (void)
	Enable RTC.
__STATIC_INLINE void	LL_RCC_DisableRTC (void)
	Disable RTC.
__STATIC_INLINE uint32_t	LL_RCC_IsEnabledRTC (void)
	Check if RTC has been enabled or not.
__STATIC_INLINE void	LL_RCC_ForceBackupDomainReset (void)
	Force the Backup domain reset.
__STATIC_INLINE void	LL_RCC_ReleaseBackupDomainReset (void)
	Release the Backup domain reset.
__STATIC_INLINE void	LL_RCC_PLL_Enable (void)
	Enable PLL.
__STATIC_INLINE void	LL_RCC_PLL_Disable (void)
	Disable PLL.
__STATIC_INLINE uint32_t	LL_RCC_PLL_IsReady (void)
	Check if PLL Ready.
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
	Configure PLL used for SYSCLK Domain.
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
	Configure PLL used for SAI domain clock.
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
	Configure PLL used for 48Mhz domain clock.
__STATIC_INLINE void	LL_RCC_PLL_SetMainSource (uint32_t PLLSource)
	Configure PLL clock source.
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetMainSource (void)
	Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetN (void)
	Get Main PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetP (void)
	Get Main PLL division factor for PLLP.
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetQ (void)
	Get Main PLL division factor for PLLQ.
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetR (void)
	Get Main PLL division factor for PLLR.
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetDivider (void)
	Get Division factor for the main PLL and other PLL.
__STATIC_INLINE void	LL_RCC_PLL_EnableDomain_SAI (void)
	Enable PLL output mapped on SAI domain clock.
__STATIC_INLINE void	LL_RCC_PLL_DisableDomain_SAI (void)
	Disable PLL output mapped on SAI domain clock.
__STATIC_INLINE uint32_t	LL_RCC_PLL_IsEnabledDomain_SAI (void)
	Check if PLL output mapped on SAI domain clock is enabled.
__STATIC_INLINE void	LL_RCC_PLL_EnableDomain_48M (void)
	Enable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void	LL_RCC_PLL_DisableDomain_48M (void)
	Disable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE uint32_t	LL_RCC_PLL_IsEnabledDomain_48M (void)
	Check if PLL output mapped on 48MHz domain clock is enabled.
__STATIC_INLINE void	LL_RCC_PLL_EnableDomain_SYS (void)
	Enable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void	LL_RCC_PLL_DisableDomain_SYS (void)
	Disable PLL output mapped on SYSCLK domain.
__STATIC_INLINE uint32_t	LL_RCC_PLL_IsEnabledDomain_SYS (void)
	Check if PLL output mapped on SYSCLK domain clock is enabled.
__STATIC_INLINE void	LL_RCC_PLLSAI1_Enable (void)
	Enable PLLSAI1.
__STATIC_INLINE void	LL_RCC_PLLSAI1_Disable (void)
	Disable PLLSAI1.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_IsReady (void)
	Check if PLLSAI1 Ready.
__STATIC_INLINE void	LL_RCC_PLLSAI1_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
	Configure PLLSAI1 used for 48Mhz domain clock.
__STATIC_INLINE void	LL_RCC_PLLSAI1_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
	Configure PLLSAI1 used for SAI domain clock.
__STATIC_INLINE void	LL_RCC_PLLSAI1_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
	Configure PLLSAI1 used for ADC domain clock.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetN (void)
	Get SAI1PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetP (void)
	Get SAI1PLL division factor for PLLSAI1P.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetQ (void)
	Get SAI1PLL division factor for PLLSAI1Q.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetR (void)
	Get PLLSAI1 division factor for PLLSAIR.
__STATIC_INLINE void	LL_RCC_PLLSAI1_EnableDomain_SAI (void)
	Enable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void	LL_RCC_PLLSAI1_DisableDomain_SAI (void)
	Disable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_IsEnabledDomain_SAI (void)
	Check if PLLSAI1 output mapped on SAI domain clock is enabled.
__STATIC_INLINE void	LL_RCC_PLLSAI1_EnableDomain_48M (void)
	Enable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void	LL_RCC_PLLSAI1_DisableDomain_48M (void)
	Disable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_IsEnabledDomain_48M (void)
	Check if PLLSAI1 output mapped on SAI domain clock is enabled.
__STATIC_INLINE void	LL_RCC_PLLSAI1_EnableDomain_ADC (void)
	Enable PLLSAI1 output mapped on ADC domain clock.
__STATIC_INLINE void	LL_RCC_PLLSAI1_DisableDomain_ADC (void)
	Disable PLLSAI1 output mapped on ADC domain clock.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_IsEnabledDomain_ADC (void)
	Check if PLLSAI1 output mapped on ADC domain clock is enabled.
__STATIC_INLINE void	LL_RCC_ClearFlag_LSIRDY (void)
	Clear LSI ready interrupt flag.
__STATIC_INLINE void	LL_RCC_ClearFlag_LSERDY (void)
	Clear LSE ready interrupt flag.
__STATIC_INLINE void	LL_RCC_ClearFlag_MSIRDY (void)
	Clear MSI ready interrupt flag.
__STATIC_INLINE void	LL_RCC_ClearFlag_HSIRDY (void)
	Clear HSI ready interrupt flag.
__STATIC_INLINE void	LL_RCC_ClearFlag_HSERDY (void)
	Clear HSE ready interrupt flag.
__STATIC_INLINE void	LL_RCC_ClearFlag_PLLRDY (void)
	Clear PLL ready interrupt flag.
__STATIC_INLINE void	LL_RCC_ClearFlag_HSI48RDY (void)
	Clear HSI48 ready interrupt flag.
__STATIC_INLINE void	LL_RCC_ClearFlag_PLLSAI1RDY (void)
	Clear PLLSAI1 ready interrupt flag.
__STATIC_INLINE void	LL_RCC_ClearFlag_HSECSS (void)
	Clear Clock security system interrupt flag.
__STATIC_INLINE void	LL_RCC_ClearFlag_LSECSS (void)
	Clear LSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_LSIRDY (void)
	Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_LSERDY (void)
	Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_MSIRDY (void)
	Check if MSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_HSIRDY (void)
	Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_HSERDY (void)
	Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_PLLRDY (void)
	Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_HSI48RDY (void)
	Check if HSI48 ready interrupt occurred or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_PLLSAI1RDY (void)
	Check if PLLSAI1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_HSECSS (void)
	Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_LSECSS (void)
	Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_FWRST (void)
	Check if RCC flag FW reset is set or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_IWDGRST (void)
	Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_LPWRRST (void)
	Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_OBLRST (void)
	Check if RCC flag is set or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_PINRST (void)
	Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_SFTRST (void)
	Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_WWDGRST (void)
	Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t	LL_RCC_IsActiveFlag_BORRST (void)
	Check if RCC flag BOR reset is set or not.
__STATIC_INLINE void	LL_RCC_ClearResetFlags (void)
	Set RMVF bit to clear the reset flags.
__STATIC_INLINE void	LL_RCC_EnableIT_LSIRDY (void)
	Enable LSI ready interrupt.
__STATIC_INLINE void	LL_RCC_EnableIT_LSERDY (void)
	Enable LSE ready interrupt.
__STATIC_INLINE void	LL_RCC_EnableIT_MSIRDY (void)
	Enable MSI ready interrupt.
__STATIC_INLINE void	LL_RCC_EnableIT_HSIRDY (void)
	Enable HSI ready interrupt.
__STATIC_INLINE void	LL_RCC_EnableIT_HSERDY (void)
	Enable HSE ready interrupt.
__STATIC_INLINE void	LL_RCC_EnableIT_PLLRDY (void)
	Enable PLL ready interrupt.
__STATIC_INLINE void	LL_RCC_EnableIT_HSI48RDY (void)
	Enable HSI48 ready interrupt.
__STATIC_INLINE void	LL_RCC_EnableIT_PLLSAI1RDY (void)
	Enable PLLSAI1 ready interrupt.
__STATIC_INLINE void	LL_RCC_EnableIT_LSECSS (void)
	Enable LSE clock security system interrupt.
__STATIC_INLINE void	LL_RCC_DisableIT_LSIRDY (void)
	Disable LSI ready interrupt.
__STATIC_INLINE void	LL_RCC_DisableIT_LSERDY (void)
	Disable LSE ready interrupt.
__STATIC_INLINE void	LL_RCC_DisableIT_MSIRDY (void)
	Disable MSI ready interrupt.
__STATIC_INLINE void	LL_RCC_DisableIT_HSIRDY (void)
	Disable HSI ready interrupt.
__STATIC_INLINE void	LL_RCC_DisableIT_HSERDY (void)
	Disable HSE ready interrupt.
__STATIC_INLINE void	LL_RCC_DisableIT_PLLRDY (void)
	Disable PLL ready interrupt.
__STATIC_INLINE void	LL_RCC_DisableIT_HSI48RDY (void)
	Disable HSI48 ready interrupt.
__STATIC_INLINE void	LL_RCC_DisableIT_PLLSAI1RDY (void)
	Disable PLLSAI1 ready interrupt.
__STATIC_INLINE void	LL_RCC_DisableIT_LSECSS (void)
	Disable LSE clock security system interrupt.
__STATIC_INLINE uint32_t	LL_RCC_IsEnabledIT_LSIRDY (void)
	Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t	LL_RCC_IsEnabledIT_LSERDY (void)
	Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t	LL_RCC_IsEnabledIT_MSIRDY (void)
	Checks if MSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t	LL_RCC_IsEnabledIT_HSIRDY (void)
	Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t	LL_RCC_IsEnabledIT_HSERDY (void)
	Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t	LL_RCC_IsEnabledIT_PLLRDY (void)
	Checks if PLL ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t	LL_RCC_IsEnabledIT_HSI48RDY (void)
	Checks if HSI48 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t	LL_RCC_IsEnabledIT_PLLSAI1RDY (void)
	Checks if PLLSAI1 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t	LL_RCC_IsEnabledIT_LSECSS (void)
	Checks if LSECSS interrupt source is enabled or disabled.
ErrorStatus	LL_RCC_DeInit (void)
	Reset the RCC clock configuration to the default reset state.
void	LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
	Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t	LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
	Return USARTx clock frequency.
uint32_t	LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
	Return I2Cx clock frequency.
uint32_t	LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
	Return LPUARTx clock frequency.
uint32_t	LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
	Return LPTIMx clock frequency.
uint32_t	LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
	Return SAIx clock frequency.
uint32_t	LL_RCC_GetSDMMCClockFreq (uint32_t SDMMCxSource)
	Return SDMMCx clock frequency.
uint32_t	LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
	Return RNGx clock frequency.
uint32_t	LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
	Return USBx clock frequency.
uint32_t	LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
	Return ADCx clock frequency.
uint32_t	LL_RCC_GetSWPMIClockFreq (uint32_t SWPMIxSource)
	Return SWPMIx clock frequency.

Detailed Description

Header file of RCC LL module.

Author:: MCD Application Team

Attention:

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32l4xx_ll_rcc.h.

Data Structures

Defines

Functions

Detailed Description