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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_rcc.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file in 00013 * the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 ****************************************************************************** 00016 */ 00017 00018 /* Define to prevent recursive inclusion -------------------------------------*/ 00019 #ifndef STM32L4xx_HAL_RCC_H 00020 #define STM32L4xx_HAL_RCC_H 00021 00022 #ifdef __cplusplus 00023 extern "C" { 00024 #endif 00025 00026 /* Includes ------------------------------------------------------------------*/ 00027 #include "stm32l4xx_hal_def.h" 00028 00029 /** @addtogroup STM32L4xx_HAL_Driver 00030 * @{ 00031 */ 00032 00033 /** @addtogroup RCC 00034 * @{ 00035 */ 00036 00037 /* Exported types ------------------------------------------------------------*/ 00038 /** @defgroup RCC_Exported_Types RCC Exported Types 00039 * @{ 00040 */ 00041 00042 /** 00043 * @brief RCC PLL configuration structure definition 00044 */ 00045 typedef struct 00046 { 00047 uint32_t PLLState; /*!< The new state of the PLL. 00048 This parameter can be a value of @ref RCC_PLL_Config */ 00049 00050 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 00051 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00052 00053 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 00054 This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 00055 This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */ 00056 00057 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 00058 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ 00059 00060 #if defined(RCC_PLLP_SUPPORT) 00061 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. 00062 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 00063 #endif /* RCC_PLLP_SUPPORT */ 00064 00065 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. 00066 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 00067 00068 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 00069 User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ 00070 on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices. 00071 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 00072 00073 }RCC_PLLInitTypeDef; 00074 00075 /** 00076 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 00077 */ 00078 typedef struct 00079 { 00080 uint32_t OscillatorType; /*!< The oscillators to be configured. 00081 This parameter can be a value of @ref RCC_Oscillator_Type */ 00082 00083 uint32_t HSEState; /*!< The new state of the HSE. 00084 This parameter can be a value of @ref RCC_HSE_Config */ 00085 00086 uint32_t LSEState; /*!< The new state of the LSE. 00087 This parameter can be a value of @ref RCC_LSE_Config */ 00088 00089 uint32_t HSIState; /*!< The new state of the HSI. 00090 This parameter can be a value of @ref RCC_HSI_Config */ 00091 00092 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 00093 This parameter must be a number between Min_Data = 0 and Max_Data = 31 on 00094 STM32L43x/STM32L44x/STM32L47x/STM32L48x devices. 00095 This parameter must be a number between Min_Data = 0 and Max_Data = 127 on 00096 the other devices */ 00097 00098 uint32_t LSIState; /*!< The new state of the LSI. 00099 This parameter can be a value of @ref RCC_LSI_Config */ 00100 #if defined(RCC_CSR_LSIPREDIV) 00101 00102 uint32_t LSIDiv; /*!< The division factor of the LSI. 00103 This parameter can be a value of @ref RCC_LSI_Div */ 00104 #endif /* RCC_CSR_LSIPREDIV */ 00105 00106 uint32_t MSIState; /*!< The new state of the MSI. 00107 This parameter can be a value of @ref RCC_MSI_Config */ 00108 00109 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 00110 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00111 00112 uint32_t MSIClockRange; /*!< The MSI frequency range. 00113 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 00114 00115 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). 00116 This parameter can be a value of @ref RCC_HSI48_Config */ 00117 00118 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 00119 00120 }RCC_OscInitTypeDef; 00121 00122 /** 00123 * @brief RCC System, AHB and APB busses clock configuration structure definition 00124 */ 00125 typedef struct 00126 { 00127 uint32_t ClockType; /*!< The clock to be configured. 00128 This parameter can be a value of @ref RCC_System_Clock_Type */ 00129 00130 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 00131 This parameter can be a value of @ref RCC_System_Clock_Source */ 00132 00133 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 00134 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 00135 00136 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 00137 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00138 00139 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 00140 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00141 00142 }RCC_ClkInitTypeDef; 00143 00144 /** 00145 * @} 00146 */ 00147 00148 /* Exported constants --------------------------------------------------------*/ 00149 /** @defgroup RCC_Exported_Constants RCC Exported Constants 00150 * @{ 00151 */ 00152 00153 /** @defgroup RCC_Timeout_Value Timeout Values 00154 * @{ 00155 */ 00156 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 00157 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 00158 /** 00159 * @} 00160 */ 00161 00162 /** @defgroup RCC_Oscillator_Type Oscillator Type 00163 * @{ 00164 */ 00165 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 00166 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 00167 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 00168 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 00169 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 00170 #define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ 00171 #if defined(RCC_HSI48_SUPPORT) 00172 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ 00173 #endif /* RCC_HSI48_SUPPORT */ 00174 /** 00175 * @} 00176 */ 00177 00178 /** @defgroup RCC_HSE_Config HSE Config 00179 * @{ 00180 */ 00181 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 00182 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 00183 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 00184 /** 00185 * @} 00186 */ 00187 00188 /** @defgroup RCC_LSE_Config LSE Config 00189 * @{ 00190 */ 00191 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 00192 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 00193 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 00194 #if defined(RCC_BDCR_LSESYSDIS) 00195 #define RCC_LSE_ON_RTC_ONLY (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */ 00196 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */ 00197 #endif /* RCC_BDCR_LSESYSDIS */ 00198 /** 00199 * @} 00200 */ 00201 00202 /** @defgroup RCC_HSI_Config HSI Config 00203 * @{ 00204 */ 00205 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 00206 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 00207 00208 #if defined(RCC_ICSCR_HSITRIM_6) 00209 #define RCC_HSICALIBRATION_DEFAULT 0x40U /*!< Default HSI calibration trimming value 64 on devices other than STM32L43x/STM32L44x/STM32L47x/STM32L48x */ 00210 #else 00211 #define RCC_HSICALIBRATION_DEFAULT 0x10U /*!< Default HSI calibration trimming value 16 on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices */ 00212 #endif /* RCC_ICSCR_HSITRIM_6 */ 00213 /** 00214 * @} 00215 */ 00216 00217 /** @defgroup RCC_LSI_Config LSI Config 00218 * @{ 00219 */ 00220 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 00221 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 00222 /** 00223 * @} 00224 */ 00225 #if defined(RCC_CSR_LSIPREDIV) 00226 00227 /** @defgroup RCC_LSI_Div LSI Div 00228 * @{ 00229 */ 00230 #define RCC_LSI_DIV1 0x00000000U /*!< LSI clock not divided */ 00231 #define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */ 00232 /** 00233 * @} 00234 */ 00235 #endif /* RCC_CSR_LSIPREDIV */ 00236 00237 /** @defgroup RCC_MSI_Config MSI Config 00238 * @{ 00239 */ 00240 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 00241 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 00242 00243 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 00244 /** 00245 * @} 00246 */ 00247 00248 #if defined(RCC_HSI48_SUPPORT) 00249 /** @defgroup RCC_HSI48_Config HSI48 Config 00250 * @{ 00251 */ 00252 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 00253 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 00254 /** 00255 * @} 00256 */ 00257 #else 00258 /** @defgroup RCC_HSI48_Config HSI48 Config 00259 * @{ 00260 */ 00261 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 00262 /** 00263 * @} 00264 */ 00265 #endif /* RCC_HSI48_SUPPORT */ 00266 00267 /** @defgroup RCC_PLL_Config PLL Config 00268 * @{ 00269 */ 00270 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 00271 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 00272 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 00273 /** 00274 * @} 00275 */ 00276 00277 #if defined(RCC_PLLP_SUPPORT) 00278 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 00279 * @{ 00280 */ 00281 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 00282 #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ 00283 #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ 00284 #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ 00285 #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ 00286 #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ 00287 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 00288 #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ 00289 #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ 00290 #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ 00291 #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ 00292 #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ 00293 #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ 00294 #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ 00295 #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ 00296 #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ 00297 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 00298 #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ 00299 #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ 00300 #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ 00301 #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ 00302 #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ 00303 #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ 00304 #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ 00305 #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ 00306 #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ 00307 #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ 00308 #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ 00309 #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ 00310 #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ 00311 #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ 00312 #else 00313 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 00314 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 00315 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 00316 /** 00317 * @} 00318 */ 00319 #endif /* RCC_PLLP_SUPPORT */ 00320 00321 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 00322 * @{ 00323 */ 00324 #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ 00325 #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ 00326 #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ 00327 #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ 00328 /** 00329 * @} 00330 */ 00331 00332 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 00333 * @{ 00334 */ 00335 #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ 00336 #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ 00337 #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ 00338 #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ 00339 /** 00340 * @} 00341 */ 00342 00343 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 00344 * @{ 00345 */ 00346 #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ 00347 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ 00348 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 00349 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 00350 /** 00351 * @} 00352 */ 00353 00354 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 00355 * @{ 00356 */ 00357 #if defined(RCC_PLLSAI2_SUPPORT) 00358 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ 00359 #elif defined(RCC_PLLSAI1_SUPPORT) 00360 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ 00361 #endif /* RCC_PLLSAI2_SUPPORT */ 00362 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ 00363 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 00364 /** 00365 * @} 00366 */ 00367 #if defined(RCC_PLLSAI1_SUPPORT) 00368 00369 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 00370 * @{ 00371 */ 00372 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 00373 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ 00374 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ 00375 /** 00376 * @} 00377 */ 00378 #endif /* RCC_PLLSAI1_SUPPORT */ 00379 00380 #if defined(RCC_PLLSAI2_SUPPORT) 00381 00382 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output 00383 * @{ 00384 */ 00385 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ 00386 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 00387 #define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */ 00388 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 00389 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 00390 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ 00391 #else 00392 #define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */ 00393 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 00394 /** 00395 * @} 00396 */ 00397 00398 #endif /* RCC_PLLSAI2_SUPPORT */ 00399 00400 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 00401 * @{ 00402 */ 00403 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ 00404 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ 00405 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ 00406 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ 00407 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ 00408 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ 00409 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ 00410 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ 00411 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ 00412 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ 00413 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ 00414 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ 00415 /** 00416 * @} 00417 */ 00418 00419 /** @defgroup RCC_System_Clock_Type System Clock Type 00420 * @{ 00421 */ 00422 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 00423 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 00424 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 00425 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 00426 /** 00427 * @} 00428 */ 00429 00430 /** @defgroup RCC_System_Clock_Source System Clock Source 00431 * @{ 00432 */ 00433 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ 00434 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 00435 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 00436 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 00437 /** 00438 * @} 00439 */ 00440 00441 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 00442 * @{ 00443 */ 00444 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 00445 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00446 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00447 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00448 /** 00449 * @} 00450 */ 00451 00452 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 00453 * @{ 00454 */ 00455 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 00456 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 00457 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 00458 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 00459 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 00460 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 00461 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 00462 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 00463 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 00464 /** 00465 * @} 00466 */ 00467 00468 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 00469 * @{ 00470 */ 00471 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 00472 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 00473 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 00474 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 00475 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 00476 /** 00477 * @} 00478 */ 00479 00480 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 00481 * @{ 00482 */ 00483 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 00484 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 00485 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 00486 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 00487 /** 00488 * @} 00489 */ 00490 00491 /** @defgroup RCC_MCO_Index MCO Index 00492 * @{ 00493 */ 00494 #define RCC_MCO1 0x00000000U 00495 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 00496 /** 00497 * @} 00498 */ 00499 00500 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 00501 * @{ 00502 */ 00503 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 00504 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 00505 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 00506 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 00507 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 00508 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ 00509 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 00510 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 00511 #if defined(RCC_HSI48_SUPPORT) 00512 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */ 00513 #endif /* RCC_HSI48_SUPPORT */ 00514 /** 00515 * @} 00516 */ 00517 00518 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 00519 * @{ 00520 */ 00521 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ 00522 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ 00523 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ 00524 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ 00525 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ 00526 /** 00527 * @} 00528 */ 00529 00530 /** @defgroup RCC_Interrupt Interrupts 00531 * @{ 00532 */ 00533 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 00534 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 00535 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 00536 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 00537 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 00538 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 00539 #if defined(RCC_PLLSAI1_SUPPORT) 00540 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 00541 #endif /* RCC_PLLSAI1_SUPPORT */ 00542 #if defined(RCC_PLLSAI2_SUPPORT) 00543 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 00544 #endif /* RCC_PLLSAI2_SUPPORT */ 00545 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 00546 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 00547 #if defined(RCC_HSI48_SUPPORT) 00548 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 00549 #endif /* RCC_HSI48_SUPPORT */ 00550 /** 00551 * @} 00552 */ 00553 00554 /** @defgroup RCC_Flag Flags 00555 * Elements values convention: XXXYYYYYb 00556 * - YYYYY : Flag position in the register 00557 * - XXX : Register index 00558 * - 001: CR register 00559 * - 010: BDCR register 00560 * - 011: CSR register 00561 * - 100: CRRCR register 00562 * @{ 00563 */ 00564 /* Flags in the CR register */ 00565 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 00566 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 00567 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 00568 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 00569 #if defined(RCC_PLLSAI1_SUPPORT) 00570 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ 00571 #endif /* RCC_PLLSAI1_SUPPORT */ 00572 #if defined(RCC_PLLSAI2_SUPPORT) 00573 #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ 00574 #endif /* RCC_PLLSAI2_SUPPORT */ 00575 00576 /* Flags in the BDCR register */ 00577 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 00578 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ 00579 00580 /* Flags in the CSR register */ 00581 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 00582 #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ 00583 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 00584 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ 00585 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 00586 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 00587 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 00588 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 00589 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 00590 00591 #if defined(RCC_HSI48_SUPPORT) 00592 /* Flags in the CRRCR register */ 00593 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 00594 #endif /* RCC_HSI48_SUPPORT */ 00595 /** 00596 * @} 00597 */ 00598 00599 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 00600 * @{ 00601 */ 00602 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 00603 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 00604 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 00605 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 00606 /** 00607 * @} 00608 */ 00609 00610 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 00611 * @{ 00612 */ 00613 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 00614 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 00615 /** 00616 * @} 00617 */ 00618 00619 /** 00620 * @} 00621 */ 00622 00623 /* Exported macros -----------------------------------------------------------*/ 00624 00625 /** @defgroup RCC_Exported_Macros RCC Exported Macros 00626 * @{ 00627 */ 00628 00629 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 00630 * @brief Enable or disable the AHB1 peripheral clock. 00631 * @note After reset, the peripheral clock (used for registers read/write access) 00632 * is disabled and the application software has to enable this clock before 00633 * using it. 00634 * @{ 00635 */ 00636 00637 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 00638 __IO uint32_t tmpreg; \ 00639 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 00640 /* Delay after an RCC peripheral clock enabling */ \ 00641 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 00642 UNUSED(tmpreg); \ 00643 } while(0) 00644 00645 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 00646 __IO uint32_t tmpreg; \ 00647 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 00648 /* Delay after an RCC peripheral clock enabling */ \ 00649 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 00650 UNUSED(tmpreg); \ 00651 } while(0) 00652 00653 #if defined(DMAMUX1) 00654 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ 00655 __IO uint32_t tmpreg; \ 00656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 00657 /* Delay after an RCC peripheral clock enabling */ \ 00658 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 00659 UNUSED(tmpreg); \ 00660 } while(0) 00661 #endif /* DMAMUX1 */ 00662 00663 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 00664 __IO uint32_t tmpreg; \ 00665 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 00666 /* Delay after an RCC peripheral clock enabling */ \ 00667 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 00668 UNUSED(tmpreg); \ 00669 } while(0) 00670 00671 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 00672 __IO uint32_t tmpreg; \ 00673 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 00674 /* Delay after an RCC peripheral clock enabling */ \ 00675 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 00676 UNUSED(tmpreg); \ 00677 } while(0) 00678 00679 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 00680 __IO uint32_t tmpreg; \ 00681 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 00682 /* Delay after an RCC peripheral clock enabling */ \ 00683 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 00684 UNUSED(tmpreg); \ 00685 } while(0) 00686 00687 #if defined(DMA2D) 00688 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 00689 __IO uint32_t tmpreg; \ 00690 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 00691 /* Delay after an RCC peripheral clock enabling */ \ 00692 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 00693 UNUSED(tmpreg); \ 00694 } while(0) 00695 #endif /* DMA2D */ 00696 00697 #if defined(GFXMMU) 00698 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ 00699 __IO uint32_t tmpreg; \ 00700 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 00701 /* Delay after an RCC peripheral clock enabling */ \ 00702 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 00703 UNUSED(tmpreg); \ 00704 } while(0) 00705 #endif /* GFXMMU */ 00706 00707 00708 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) 00709 00710 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) 00711 00712 #if defined(DMAMUX1) 00713 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) 00714 #endif /* DMAMUX1 */ 00715 00716 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 00717 00718 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 00719 00720 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 00721 00722 #if defined(DMA2D) 00723 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) 00724 #endif /* DMA2D */ 00725 00726 #if defined(GFXMMU) 00727 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) 00728 #endif /* GFXMMU */ 00729 00730 /** 00731 * @} 00732 */ 00733 00734 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 00735 * @brief Enable or disable the AHB2 peripheral clock. 00736 * @note After reset, the peripheral clock (used for registers read/write access) 00737 * is disabled and the application software has to enable this clock before 00738 * using it. 00739 * @{ 00740 */ 00741 00742 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 00743 __IO uint32_t tmpreg; \ 00744 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 00745 /* Delay after an RCC peripheral clock enabling */ \ 00746 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 00747 UNUSED(tmpreg); \ 00748 } while(0) 00749 00750 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 00751 __IO uint32_t tmpreg; \ 00752 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 00753 /* Delay after an RCC peripheral clock enabling */ \ 00754 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 00755 UNUSED(tmpreg); \ 00756 } while(0) 00757 00758 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 00759 __IO uint32_t tmpreg; \ 00760 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 00761 /* Delay after an RCC peripheral clock enabling */ \ 00762 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 00763 UNUSED(tmpreg); \ 00764 } while(0) 00765 00766 #if defined(GPIOD) 00767 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 00768 __IO uint32_t tmpreg; \ 00769 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 00770 /* Delay after an RCC peripheral clock enabling */ \ 00771 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 00772 UNUSED(tmpreg); \ 00773 } while(0) 00774 #endif /* GPIOD */ 00775 00776 #if defined(GPIOE) 00777 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 00778 __IO uint32_t tmpreg; \ 00779 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 00780 /* Delay after an RCC peripheral clock enabling */ \ 00781 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 00782 UNUSED(tmpreg); \ 00783 } while(0) 00784 #endif /* GPIOE */ 00785 00786 #if defined(GPIOF) 00787 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 00788 __IO uint32_t tmpreg; \ 00789 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 00790 /* Delay after an RCC peripheral clock enabling */ \ 00791 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 00792 UNUSED(tmpreg); \ 00793 } while(0) 00794 #endif /* GPIOF */ 00795 00796 #if defined(GPIOG) 00797 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 00798 __IO uint32_t tmpreg; \ 00799 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 00800 /* Delay after an RCC peripheral clock enabling */ \ 00801 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 00802 UNUSED(tmpreg); \ 00803 } while(0) 00804 #endif /* GPIOG */ 00805 00806 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 00807 __IO uint32_t tmpreg; \ 00808 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 00809 /* Delay after an RCC peripheral clock enabling */ \ 00810 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 00811 UNUSED(tmpreg); \ 00812 } while(0) 00813 00814 #if defined(GPIOI) 00815 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 00816 __IO uint32_t tmpreg; \ 00817 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 00818 /* Delay after an RCC peripheral clock enabling */ \ 00819 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 00820 UNUSED(tmpreg); \ 00821 } while(0) 00822 #endif /* GPIOI */ 00823 00824 #if defined(USB_OTG_FS) 00825 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 00826 __IO uint32_t tmpreg; \ 00827 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 00828 /* Delay after an RCC peripheral clock enabling */ \ 00829 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 00830 UNUSED(tmpreg); \ 00831 } while(0) 00832 #endif /* USB_OTG_FS */ 00833 00834 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 00835 __IO uint32_t tmpreg; \ 00836 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 00837 /* Delay after an RCC peripheral clock enabling */ \ 00838 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 00839 UNUSED(tmpreg); \ 00840 } while(0) 00841 00842 #if defined(DCMI) 00843 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 00844 __IO uint32_t tmpreg; \ 00845 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ 00846 /* Delay after an RCC peripheral clock enabling */ \ 00847 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ 00848 UNUSED(tmpreg); \ 00849 } while(0) 00850 #endif /* DCMI */ 00851 00852 #if defined(PKA) 00853 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 00854 __IO uint32_t tmpreg; \ 00855 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 00856 /* Delay after an RCC peripheral clock enabling */ \ 00857 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 00858 UNUSED(tmpreg); \ 00859 } while(0) 00860 #endif /* PKA */ 00861 00862 #if defined(AES) 00863 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 00864 __IO uint32_t tmpreg; \ 00865 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 00866 /* Delay after an RCC peripheral clock enabling */ \ 00867 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 00868 UNUSED(tmpreg); \ 00869 } while(0) 00870 #endif /* AES */ 00871 00872 #if defined(HASH) 00873 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 00874 __IO uint32_t tmpreg; \ 00875 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 00876 /* Delay after an RCC peripheral clock enabling */ \ 00877 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 00878 UNUSED(tmpreg); \ 00879 } while(0) 00880 #endif /* HASH */ 00881 00882 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 00883 __IO uint32_t tmpreg; \ 00884 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 00885 /* Delay after an RCC peripheral clock enabling */ \ 00886 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 00887 UNUSED(tmpreg); \ 00888 } while(0) 00889 00890 #if defined(OCTOSPIM) 00891 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ 00892 __IO uint32_t tmpreg; \ 00893 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ 00894 /* Delay after an RCC peripheral clock enabling */ \ 00895 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ 00896 UNUSED(tmpreg); \ 00897 } while(0) 00898 #endif /* OCTOSPIM */ 00899 00900 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 00901 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 00902 __IO uint32_t tmpreg; \ 00903 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 00904 /* Delay after an RCC peripheral clock enabling */ \ 00905 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 00906 UNUSED(tmpreg); \ 00907 } while(0) 00908 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 00909 00910 #if defined(SDMMC2) 00911 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 00912 __IO uint32_t tmpreg; \ 00913 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN); \ 00914 /* Delay after an RCC peripheral clock enabling */ \ 00915 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN); \ 00916 UNUSED(tmpreg); \ 00917 } while(0) 00918 #endif /* SDMMC2 */ 00919 00920 00921 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 00922 00923 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 00924 00925 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 00926 00927 #if defined(GPIOD) 00928 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 00929 #endif /* GPIOD */ 00930 00931 #if defined(GPIOE) 00932 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 00933 #endif /* GPIOE */ 00934 00935 #if defined(GPIOF) 00936 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 00937 #endif /* GPIOF */ 00938 00939 #if defined(GPIOG) 00940 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 00941 #endif /* GPIOG */ 00942 00943 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 00944 00945 #if defined(GPIOI) 00946 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) 00947 #endif /* GPIOI */ 00948 00949 #if defined(USB_OTG_FS) 00950 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); 00951 #endif /* USB_OTG_FS */ 00952 00953 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) 00954 00955 #if defined(DCMI) 00956 #define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) 00957 #endif /* DCMI */ 00958 00959 #if defined(PKA) 00960 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) 00961 #endif /* PKA */ 00962 00963 #if defined(AES) 00964 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 00965 #endif /* AES */ 00966 00967 #if defined(HASH) 00968 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 00969 #endif /* HASH */ 00970 00971 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 00972 00973 #if defined(OCTOSPIM) 00974 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) 00975 #endif /* OCTOSPIM */ 00976 00977 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 00978 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) 00979 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 00980 00981 #if defined(SDMMC2) 00982 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) 00983 #endif /* SDMMC2 */ 00984 00985 /** 00986 * @} 00987 */ 00988 00989 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 00990 * @brief Enable or disable the AHB3 peripheral clock. 00991 * @note After reset, the peripheral clock (used for registers read/write access) 00992 * is disabled and the application software has to enable this clock before 00993 * using it. 00994 * @{ 00995 */ 00996 00997 #if defined(FMC_BANK1) 00998 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 00999 __IO uint32_t tmpreg; \ 01000 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 01001 /* Delay after an RCC peripheral clock enabling */ \ 01002 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 01003 UNUSED(tmpreg); \ 01004 } while(0) 01005 #endif /* FMC_BANK1 */ 01006 01007 #if defined(QUADSPI) 01008 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 01009 __IO uint32_t tmpreg; \ 01010 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 01011 /* Delay after an RCC peripheral clock enabling */ \ 01012 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 01013 UNUSED(tmpreg); \ 01014 } while(0) 01015 #endif /* QUADSPI */ 01016 01017 #if defined(OCTOSPI1) 01018 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 01019 __IO uint32_t tmpreg; \ 01020 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 01021 /* Delay after an RCC peripheral clock enabling */ \ 01022 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 01023 UNUSED(tmpreg); \ 01024 } while(0) 01025 #endif /* OCTOSPI1 */ 01026 01027 #if defined(OCTOSPI2) 01028 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 01029 __IO uint32_t tmpreg; \ 01030 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ 01031 /* Delay after an RCC peripheral clock enabling */ \ 01032 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ 01033 UNUSED(tmpreg); \ 01034 } while(0) 01035 #endif /* OCTOSPI2 */ 01036 01037 #if defined(FMC_BANK1) 01038 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) 01039 #endif /* FMC_BANK1 */ 01040 01041 #if defined(QUADSPI) 01042 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) 01043 #endif /* QUADSPI */ 01044 01045 #if defined(OCTOSPI1) 01046 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) 01047 #endif /* OCTOSPI1 */ 01048 01049 #if defined(OCTOSPI2) 01050 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) 01051 #endif /* OCTOSPI2 */ 01052 01053 /** 01054 * @} 01055 */ 01056 01057 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 01058 * @brief Enable or disable the APB1 peripheral clock. 01059 * @note After reset, the peripheral clock (used for registers read/write access) 01060 * is disabled and the application software has to enable this clock before 01061 * using it. 01062 * @{ 01063 */ 01064 01065 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 01066 __IO uint32_t tmpreg; \ 01067 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 01068 /* Delay after an RCC peripheral clock enabling */ \ 01069 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 01070 UNUSED(tmpreg); \ 01071 } while(0) 01072 01073 #if defined(TIM3) 01074 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 01075 __IO uint32_t tmpreg; \ 01076 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 01077 /* Delay after an RCC peripheral clock enabling */ \ 01078 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 01079 UNUSED(tmpreg); \ 01080 } while(0) 01081 #endif /* TIM3 */ 01082 01083 #if defined(TIM4) 01084 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 01085 __IO uint32_t tmpreg; \ 01086 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 01087 /* Delay after an RCC peripheral clock enabling */ \ 01088 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 01089 UNUSED(tmpreg); \ 01090 } while(0) 01091 #endif /* TIM4 */ 01092 01093 #if defined(TIM5) 01094 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 01095 __IO uint32_t tmpreg; \ 01096 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 01097 /* Delay after an RCC peripheral clock enabling */ \ 01098 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 01099 UNUSED(tmpreg); \ 01100 } while(0) 01101 #endif /* TIM5 */ 01102 01103 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 01104 __IO uint32_t tmpreg; \ 01105 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 01106 /* Delay after an RCC peripheral clock enabling */ \ 01107 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 01108 UNUSED(tmpreg); \ 01109 } while(0) 01110 01111 #if defined(TIM7) 01112 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 01113 __IO uint32_t tmpreg; \ 01114 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 01115 /* Delay after an RCC peripheral clock enabling */ \ 01116 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 01117 UNUSED(tmpreg); \ 01118 } while(0) 01119 #endif /* TIM7 */ 01120 01121 #if defined(LCD) 01122 #define __HAL_RCC_LCD_CLK_ENABLE() do { \ 01123 __IO uint32_t tmpreg; \ 01124 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 01125 /* Delay after an RCC peripheral clock enabling */ \ 01126 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 01127 UNUSED(tmpreg); \ 01128 } while(0) 01129 #endif /* LCD */ 01130 01131 #if defined(RCC_APB1ENR1_RTCAPBEN) 01132 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 01133 __IO uint32_t tmpreg; \ 01134 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 01135 /* Delay after an RCC peripheral clock enabling */ \ 01136 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 01137 UNUSED(tmpreg); \ 01138 } while(0) 01139 #endif /* RCC_APB1ENR1_RTCAPBEN */ 01140 01141 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 01142 __IO uint32_t tmpreg; \ 01143 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 01144 /* Delay after an RCC peripheral clock enabling */ \ 01145 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 01146 UNUSED(tmpreg); \ 01147 } while(0) 01148 01149 #if defined(SPI2) 01150 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 01151 __IO uint32_t tmpreg; \ 01152 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 01153 /* Delay after an RCC peripheral clock enabling */ \ 01154 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 01155 UNUSED(tmpreg); \ 01156 } while(0) 01157 #endif /* SPI2 */ 01158 01159 #if defined(SPI3) 01160 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 01161 __IO uint32_t tmpreg; \ 01162 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 01163 /* Delay after an RCC peripheral clock enabling */ \ 01164 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 01165 UNUSED(tmpreg); \ 01166 } while(0) 01167 #endif /* SPI3 */ 01168 01169 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 01170 __IO uint32_t tmpreg; \ 01171 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 01172 /* Delay after an RCC peripheral clock enabling */ \ 01173 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 01174 UNUSED(tmpreg); \ 01175 } while(0) 01176 01177 #if defined(USART3) 01178 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 01179 __IO uint32_t tmpreg; \ 01180 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 01181 /* Delay after an RCC peripheral clock enabling */ \ 01182 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 01183 UNUSED(tmpreg); \ 01184 } while(0) 01185 #endif /* USART3 */ 01186 01187 #if defined(UART4) 01188 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 01189 __IO uint32_t tmpreg; \ 01190 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 01191 /* Delay after an RCC peripheral clock enabling */ \ 01192 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 01193 UNUSED(tmpreg); \ 01194 } while(0) 01195 #endif /* UART4 */ 01196 01197 #if defined(UART5) 01198 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 01199 __IO uint32_t tmpreg; \ 01200 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 01201 /* Delay after an RCC peripheral clock enabling */ \ 01202 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 01203 UNUSED(tmpreg); \ 01204 } while(0) 01205 #endif /* UART5 */ 01206 01207 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 01208 __IO uint32_t tmpreg; \ 01209 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 01210 /* Delay after an RCC peripheral clock enabling */ \ 01211 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 01212 UNUSED(tmpreg); \ 01213 } while(0) 01214 01215 #if defined(I2C2) 01216 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 01217 __IO uint32_t tmpreg; \ 01218 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 01219 /* Delay after an RCC peripheral clock enabling */ \ 01220 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 01221 UNUSED(tmpreg); \ 01222 } while(0) 01223 #endif /* I2C2 */ 01224 01225 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 01226 __IO uint32_t tmpreg; \ 01227 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 01228 /* Delay after an RCC peripheral clock enabling */ \ 01229 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 01230 UNUSED(tmpreg); \ 01231 } while(0) 01232 01233 #if defined(I2C4) 01234 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 01235 __IO uint32_t tmpreg; \ 01236 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 01237 /* Delay after an RCC peripheral clock enabling */ \ 01238 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 01239 UNUSED(tmpreg); \ 01240 } while(0) 01241 #endif /* I2C4 */ 01242 01243 #if defined(CRS) 01244 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 01245 __IO uint32_t tmpreg; \ 01246 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 01247 /* Delay after an RCC peripheral clock enabling */ \ 01248 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 01249 UNUSED(tmpreg); \ 01250 } while(0) 01251 #endif /* CRS */ 01252 01253 #if defined(CAN1) 01254 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 01255 __IO uint32_t tmpreg; \ 01256 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 01257 /* Delay after an RCC peripheral clock enabling */ \ 01258 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 01259 UNUSED(tmpreg); \ 01260 } while(0) 01261 #endif /* CAN1 */ 01262 01263 #if defined(CAN2) 01264 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 01265 __IO uint32_t tmpreg; \ 01266 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ 01267 /* Delay after an RCC peripheral clock enabling */ \ 01268 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ 01269 UNUSED(tmpreg); \ 01270 } while(0) 01271 #endif /* CAN2 */ 01272 01273 #if defined(USB) 01274 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 01275 __IO uint32_t tmpreg; \ 01276 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 01277 /* Delay after an RCC peripheral clock enabling */ \ 01278 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 01279 UNUSED(tmpreg); \ 01280 } while(0) 01281 #endif /* USB */ 01282 01283 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 01284 __IO uint32_t tmpreg; \ 01285 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 01286 /* Delay after an RCC peripheral clock enabling */ \ 01287 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 01288 UNUSED(tmpreg); \ 01289 } while(0) 01290 01291 #if defined(DAC1) 01292 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 01293 __IO uint32_t tmpreg; \ 01294 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 01295 /* Delay after an RCC peripheral clock enabling */ \ 01296 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 01297 UNUSED(tmpreg); \ 01298 } while(0) 01299 #endif /* DAC1 */ 01300 01301 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 01302 __IO uint32_t tmpreg; \ 01303 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 01304 /* Delay after an RCC peripheral clock enabling */ \ 01305 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 01306 UNUSED(tmpreg); \ 01307 } while(0) 01308 01309 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 01310 __IO uint32_t tmpreg; \ 01311 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 01312 /* Delay after an RCC peripheral clock enabling */ \ 01313 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 01314 UNUSED(tmpreg); \ 01315 } while(0) 01316 01317 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 01318 __IO uint32_t tmpreg; \ 01319 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 01320 /* Delay after an RCC peripheral clock enabling */ \ 01321 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 01322 UNUSED(tmpreg); \ 01323 } while(0) 01324 01325 #if defined(SWPMI1) 01326 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ 01327 __IO uint32_t tmpreg; \ 01328 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 01329 /* Delay after an RCC peripheral clock enabling */ \ 01330 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 01331 UNUSED(tmpreg); \ 01332 } while(0) 01333 #endif /* SWPMI1 */ 01334 01335 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 01336 __IO uint32_t tmpreg; \ 01337 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 01338 /* Delay after an RCC peripheral clock enabling */ \ 01339 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 01340 UNUSED(tmpreg); \ 01341 } while(0) 01342 01343 01344 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 01345 01346 #if defined(TIM3) 01347 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 01348 #endif /* TIM3 */ 01349 01350 #if defined(TIM4) 01351 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 01352 #endif /* TIM4 */ 01353 01354 #if defined(TIM5) 01355 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 01356 #endif /* TIM5 */ 01357 01358 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 01359 01360 #if defined(TIM7) 01361 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 01362 #endif /* TIM7 */ 01363 01364 #if defined(LCD) 01365 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); 01366 #endif /* LCD */ 01367 01368 #if defined(RCC_APB1ENR1_RTCAPBEN) 01369 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); 01370 #endif /* RCC_APB1ENR1_RTCAPBEN */ 01371 01372 #if defined(SPI2) 01373 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 01374 #endif /* SPI2 */ 01375 01376 #if defined(SPI3) 01377 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) 01378 #endif /* SPI3 */ 01379 01380 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 01381 01382 #if defined(USART3) 01383 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 01384 #endif /* USART3 */ 01385 01386 #if defined(UART4) 01387 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 01388 #endif /* UART4 */ 01389 01390 #if defined(UART5) 01391 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 01392 #endif /* UART5 */ 01393 01394 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 01395 01396 #if defined(I2C2) 01397 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 01398 #endif /* I2C2 */ 01399 01400 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) 01401 01402 #if defined(I2C4) 01403 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 01404 #endif /* I2C4 */ 01405 01406 #if defined(CRS) 01407 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); 01408 #endif /* CRS */ 01409 01410 #if defined(CAN1) 01411 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) 01412 #endif /* CAN1 */ 01413 01414 #if defined(CAN2) 01415 #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) 01416 #endif /* CAN2 */ 01417 01418 #if defined(USB) 01419 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); 01420 #endif /* USB */ 01421 01422 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) 01423 01424 #if defined(DAC1) 01425 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) 01426 #endif /* DAC1 */ 01427 01428 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) 01429 01430 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) 01431 01432 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) 01433 01434 #if defined(SWPMI1) 01435 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) 01436 #endif /* SWPMI1 */ 01437 01438 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 01439 01440 /** 01441 * @} 01442 */ 01443 01444 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 01445 * @brief Enable or disable the APB2 peripheral clock. 01446 * @note After reset, the peripheral clock (used for registers read/write access) 01447 * is disabled and the application software has to enable this clock before 01448 * using it. 01449 * @{ 01450 */ 01451 01452 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 01453 __IO uint32_t tmpreg; \ 01454 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 01455 /* Delay after an RCC peripheral clock enabling */ \ 01456 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 01457 UNUSED(tmpreg); \ 01458 } while(0) 01459 01460 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \ 01461 __IO uint32_t tmpreg; \ 01462 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 01463 /* Delay after an RCC peripheral clock enabling */ \ 01464 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 01465 UNUSED(tmpreg); \ 01466 } while(0) 01467 01468 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 01469 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 01470 __IO uint32_t tmpreg; \ 01471 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 01472 /* Delay after an RCC peripheral clock enabling */ \ 01473 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 01474 UNUSED(tmpreg); \ 01475 } while(0) 01476 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 01477 01478 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 01479 __IO uint32_t tmpreg; \ 01480 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 01481 /* Delay after an RCC peripheral clock enabling */ \ 01482 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 01483 UNUSED(tmpreg); \ 01484 } while(0) 01485 01486 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 01487 __IO uint32_t tmpreg; \ 01488 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 01489 /* Delay after an RCC peripheral clock enabling */ \ 01490 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 01491 UNUSED(tmpreg); \ 01492 } while(0) 01493 01494 #if defined(TIM8) 01495 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 01496 __IO uint32_t tmpreg; \ 01497 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 01498 /* Delay after an RCC peripheral clock enabling */ \ 01499 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 01500 UNUSED(tmpreg); \ 01501 } while(0) 01502 #endif /* TIM8 */ 01503 01504 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 01505 __IO uint32_t tmpreg; \ 01506 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 01507 /* Delay after an RCC peripheral clock enabling */ \ 01508 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 01509 UNUSED(tmpreg); \ 01510 } while(0) 01511 01512 01513 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 01514 __IO uint32_t tmpreg; \ 01515 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 01516 /* Delay after an RCC peripheral clock enabling */ \ 01517 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 01518 UNUSED(tmpreg); \ 01519 } while(0) 01520 01521 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 01522 __IO uint32_t tmpreg; \ 01523 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 01524 /* Delay after an RCC peripheral clock enabling */ \ 01525 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 01526 UNUSED(tmpreg); \ 01527 } while(0) 01528 01529 #if defined(TIM17) 01530 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 01531 __IO uint32_t tmpreg; \ 01532 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 01533 /* Delay after an RCC peripheral clock enabling */ \ 01534 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 01535 UNUSED(tmpreg); \ 01536 } while(0) 01537 #endif /* TIM17 */ 01538 01539 #if defined(SAI1) 01540 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 01541 __IO uint32_t tmpreg; \ 01542 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 01543 /* Delay after an RCC peripheral clock enabling */ \ 01544 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 01545 UNUSED(tmpreg); \ 01546 } while(0) 01547 #endif /* SAI1 */ 01548 01549 #if defined(SAI2) 01550 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 01551 __IO uint32_t tmpreg; \ 01552 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 01553 /* Delay after an RCC peripheral clock enabling */ \ 01554 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 01555 UNUSED(tmpreg); \ 01556 } while(0) 01557 #endif /* SAI2 */ 01558 01559 #if defined(DFSDM1_Filter0) 01560 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 01561 __IO uint32_t tmpreg; \ 01562 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 01563 /* Delay after an RCC peripheral clock enabling */ \ 01564 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 01565 UNUSED(tmpreg); \ 01566 } while(0) 01567 #endif /* DFSDM1_Filter0 */ 01568 01569 #if defined(LTDC) 01570 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 01571 __IO uint32_t tmpreg; \ 01572 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 01573 /* Delay after an RCC peripheral clock enabling */ \ 01574 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 01575 UNUSED(tmpreg); \ 01576 } while(0) 01577 #endif /* LTDC */ 01578 01579 #if defined(DSI) 01580 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 01581 __IO uint32_t tmpreg; \ 01582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ 01583 /* Delay after an RCC peripheral clock enabling */ \ 01584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ 01585 UNUSED(tmpreg); \ 01586 } while(0) 01587 #endif /* DSI */ 01588 01589 01590 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) 01591 01592 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 01593 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) 01594 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 01595 01596 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 01597 01598 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 01599 01600 #if defined(TIM8) 01601 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 01602 #endif /* TIM8 */ 01603 01604 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 01605 01606 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 01607 01608 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 01609 01610 #if defined(TIM17) 01611 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 01612 #endif /* TIM17 */ 01613 01614 #if defined(SAI1) 01615 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 01616 #endif /* SAI1 */ 01617 01618 #if defined(SAI2) 01619 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 01620 #endif /* SAI2 */ 01621 01622 #if defined(DFSDM1_Filter0) 01623 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) 01624 #endif /* DFSDM1_Filter0 */ 01625 01626 #if defined(LTDC) 01627 #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) 01628 #endif /* LTDC */ 01629 01630 #if defined(DSI) 01631 #define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) 01632 #endif /* DSI */ 01633 01634 /** 01635 * @} 01636 */ 01637 01638 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 01639 * @brief Check whether the AHB1 peripheral clock is enabled or not. 01640 * @note After reset, the peripheral clock (used for registers read/write access) 01641 * is disabled and the application software has to enable this clock before 01642 * using it. 01643 * @{ 01644 */ 01645 01646 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) 01647 01648 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) 01649 01650 #if defined(DMAMUX1) 01651 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) 01652 #endif /* DMAMUX1 */ 01653 01654 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 01655 01656 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 01657 01658 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 01659 01660 #if defined(DMA2D) 01661 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) 01662 #endif /* DMA2D */ 01663 01664 #if defined(GFXMMU) 01665 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) 01666 #endif /* GFXMMU */ 01667 01668 01669 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) 01670 01671 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) 01672 01673 #if defined(DMAMUX1) 01674 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) 01675 #endif /* DMAMUX1 */ 01676 01677 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 01678 01679 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 01680 01681 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) 01682 01683 #if defined(DMA2D) 01684 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) 01685 #endif /* DMA2D */ 01686 01687 #if defined(GFXMMU) 01688 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) 01689 #endif /* GFXMMU */ 01690 01691 /** 01692 * @} 01693 */ 01694 01695 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 01696 * @brief Check whether the AHB2 peripheral clock is enabled or not. 01697 * @note After reset, the peripheral clock (used for registers read/write access) 01698 * is disabled and the application software has to enable this clock before 01699 * using it. 01700 * @{ 01701 */ 01702 01703 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 01704 01705 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) 01706 01707 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 01708 01709 #if defined(GPIOD) 01710 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) 01711 #endif /* GPIOD */ 01712 01713 #if defined(GPIOE) 01714 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) 01715 #endif /* GPIOE */ 01716 01717 #if defined(GPIOF) 01718 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) 01719 #endif /* GPIOF */ 01720 01721 #if defined(GPIOG) 01722 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) 01723 #endif /* GPIOG */ 01724 01725 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) 01726 01727 #if defined(GPIOI) 01728 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U) 01729 #endif /* GPIOI */ 01730 01731 #if defined(USB_OTG_FS) 01732 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U) 01733 #endif /* USB_OTG_FS */ 01734 01735 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) 01736 01737 #if defined(DCMI) 01738 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U) 01739 #endif /* DCMI */ 01740 01741 #if defined(PKA) 01742 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) 01743 #endif /* PKA */ 01744 01745 #if defined(AES) 01746 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 01747 #endif /* AES */ 01748 01749 #if defined(HASH) 01750 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) 01751 #endif /* HASH */ 01752 01753 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 01754 01755 #if defined(OCTOSPIM) 01756 #define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) != 0U) 01757 #endif /* OCTOSPIM */ 01758 01759 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 01760 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) != 0U) 01761 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 01762 01763 #if defined(SDMMC2) 01764 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) != 0U) 01765 #endif /* SDMMC2 */ 01766 01767 01768 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) 01769 01770 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) 01771 01772 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) 01773 01774 #if defined(GPIOD) 01775 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) 01776 #endif /* GPIOD */ 01777 01778 #if defined(GPIOE) 01779 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) 01780 #endif /* GPIOE */ 01781 01782 #if defined(GPIOF) 01783 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) 01784 #endif /* GPIOF */ 01785 01786 #if defined(GPIOG) 01787 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) 01788 #endif /* GPIOG */ 01789 01790 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) 01791 01792 #if defined(GPIOI) 01793 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U) 01794 #endif /* GPIOI */ 01795 01796 #if defined(USB_OTG_FS) 01797 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U) 01798 #endif /* USB_OTG_FS */ 01799 01800 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) 01801 01802 #if defined(DCMI) 01803 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U) 01804 #endif /* DCMI */ 01805 01806 #if defined(PKA) 01807 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U) 01808 #endif /* PKA */ 01809 01810 #if defined(AES) 01811 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) 01812 #endif /* AES */ 01813 01814 #if defined(HASH) 01815 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) 01816 #endif /* HASH */ 01817 01818 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) 01819 01820 #if defined(OCTOSPIM) 01821 #define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) == 0U) 01822 #endif /* OCTOSPIM */ 01823 01824 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 01825 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) == 0U) 01826 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 01827 01828 #if defined(SDMMC2) 01829 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) == 0U) 01830 #endif /* SDMMC2 */ 01831 01832 /** 01833 * @} 01834 */ 01835 01836 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 01837 * @brief Check whether the AHB3 peripheral clock is enabled or not. 01838 * @note After reset, the peripheral clock (used for registers read/write access) 01839 * is disabled and the application software has to enable this clock before 01840 * using it. 01841 * @{ 01842 */ 01843 01844 #if defined(FMC_BANK1) 01845 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) 01846 #endif /* FMC_BANK1 */ 01847 01848 #if defined(QUADSPI) 01849 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U) 01850 #endif /* QUADSPI */ 01851 01852 #if defined(OCTOSPI1) 01853 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) != 0U) 01854 #endif /* OCTOSPI1 */ 01855 01856 #if defined(OCTOSPI2) 01857 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) != 0U) 01858 #endif /* OCTOSPI2 */ 01859 01860 #if defined(FMC_BANK1) 01861 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) 01862 #endif /* FMC_BANK1 */ 01863 01864 #if defined(QUADSPI) 01865 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U) 01866 #endif /* QUADSPI */ 01867 01868 #if defined(OCTOSPI1) 01869 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) == 0U) 01870 #endif /* OCTOSPI1 */ 01871 01872 #if defined(OCTOSPI2) 01873 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) == 0U) 01874 #endif /* OCTOSPI2 */ 01875 01876 /** 01877 * @} 01878 */ 01879 01880 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 01881 * @brief Check whether the APB1 peripheral clock is enabled or not. 01882 * @note After reset, the peripheral clock (used for registers read/write access) 01883 * is disabled and the application software has to enable this clock before 01884 * using it. 01885 * @{ 01886 */ 01887 01888 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 01889 01890 #if defined(TIM3) 01891 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 01892 #endif /* TIM3 */ 01893 01894 #if defined(TIM4) 01895 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 01896 #endif /* TIM4 */ 01897 01898 #if defined(TIM5) 01899 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 01900 #endif /* TIM5 */ 01901 01902 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 01903 01904 #if defined(TIM7) 01905 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 01906 #endif /* TIM7 */ 01907 01908 #if defined(LCD) 01909 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U) 01910 #endif /* LCD */ 01911 01912 #if defined(RCC_APB1ENR1_RTCAPBEN) 01913 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) 01914 #endif /* RCC_APB1ENR1_RTCAPBEN */ 01915 01916 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 01917 01918 #if defined(SPI2) 01919 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 01920 #endif /* SPI2 */ 01921 01922 #if defined(SPI3) 01923 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) 01924 #endif /* SPI3 */ 01925 01926 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 01927 01928 #if defined(USART3) 01929 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 01930 #endif /* USART3 */ 01931 01932 #if defined(UART4) 01933 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 01934 #endif /* UART4 */ 01935 01936 #if defined(UART5) 01937 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 01938 #endif /* UART5 */ 01939 01940 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 01941 01942 #if defined(I2C2) 01943 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 01944 #endif /* I2C2 */ 01945 01946 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) 01947 01948 #if defined(I2C4) 01949 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 01950 #endif /* I2C4 */ 01951 01952 #if defined(CRS) 01953 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 01954 #endif /* CRS */ 01955 01956 #if defined(CAN1) 01957 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U) 01958 #endif /* CAN1 */ 01959 01960 #if defined(CAN2) 01961 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U) 01962 #endif /* CAN2 */ 01963 01964 #if defined(USB) 01965 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U) 01966 #endif /* USB */ 01967 01968 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) 01969 01970 #if defined(DAC1) 01971 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U) 01972 #endif /* DAC1 */ 01973 01974 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U) 01975 01976 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) 01977 01978 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) 01979 01980 #if defined(SWPMI1) 01981 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U) 01982 #endif /* SWPMI1 */ 01983 01984 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 01985 01986 01987 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 01988 01989 #if defined(TIM3) 01990 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 01991 #endif /* TIM3 */ 01992 01993 #if defined(TIM4) 01994 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 01995 #endif /* TIM4 */ 01996 01997 #if defined(TIM5) 01998 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 01999 #endif /* TIM5 */ 02000 02001 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 02002 02003 #if defined(TIM7) 02004 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 02005 #endif /* TIM7 */ 02006 02007 #if defined(LCD) 02008 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U) 02009 #endif /* LCD */ 02010 02011 #if defined(RCC_APB1ENR1_RTCAPBEN) 02012 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) 02013 #endif /* RCC_APB1ENR1_RTCAPBEN */ 02014 02015 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) 02016 02017 #if defined(SPI2) 02018 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 02019 #endif /* SPI2 */ 02020 02021 #if defined(SPI3) 02022 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) 02023 #endif /* SPI3 */ 02024 02025 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 02026 02027 #if defined(USART3) 02028 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 02029 #endif /* USART3 */ 02030 02031 #if defined(UART4) 02032 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 02033 #endif /* UART4 */ 02034 02035 #if defined(UART5) 02036 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 02037 #endif /* UART5 */ 02038 02039 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 02040 02041 #if defined(I2C2) 02042 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 02043 #endif /* I2C2 */ 02044 02045 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) 02046 02047 #if defined(I2C4) 02048 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 02049 #endif /* I2C4 */ 02050 02051 #if defined(CRS) 02052 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 02053 #endif /* CRS */ 02054 02055 #if defined(CAN1) 02056 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U) 02057 #endif /* CAN1 */ 02058 02059 #if defined(CAN2) 02060 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U) 02061 #endif /* CAN2 */ 02062 02063 #if defined(USB) 02064 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U) 02065 #endif /* USB */ 02066 02067 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) 02068 02069 #if defined(DAC1) 02070 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U) 02071 #endif /* DAC1 */ 02072 02073 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U) 02074 02075 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) 02076 02077 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) 02078 02079 #if defined(SWPMI1) 02080 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U) 02081 #endif /* SWPMI1 */ 02082 02083 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) 02084 02085 /** 02086 * @} 02087 */ 02088 02089 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 02090 * @brief Check whether the APB2 peripheral clock is enabled or not. 02091 * @note After reset, the peripheral clock (used for registers read/write access) 02092 * is disabled and the application software has to enable this clock before 02093 * using it. 02094 * @{ 02095 */ 02096 02097 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) 02098 02099 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U) 02100 02101 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 02102 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U) 02103 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 02104 02105 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 02106 02107 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 02108 02109 #if defined(TIM8) 02110 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 02111 #endif /* TIM8 */ 02112 02113 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 02114 02115 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 02116 02117 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 02118 02119 #if defined(TIM17) 02120 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 02121 #endif /* TIM17 */ 02122 02123 #if defined(SAI1) 02124 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 02125 #endif /* SAI1 */ 02126 02127 #if defined(SAI2) 02128 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 02129 #endif /* SAI2 */ 02130 02131 #if defined(DFSDM1_Filter0) 02132 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U) 02133 #endif /* DFSDM1_Filter0 */ 02134 02135 #if defined(LTDC) 02136 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) 02137 #endif /* LTDC */ 02138 02139 #if defined(DSI) 02140 #define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U) 02141 #endif /* DSI */ 02142 02143 02144 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) 02145 02146 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 02147 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U) 02148 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 02149 02150 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 02151 02152 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 02153 02154 #if defined(TIM8) 02155 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 02156 #endif /* TIM8 */ 02157 02158 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 02159 02160 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 02161 02162 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 02163 02164 #if defined(TIM17) 02165 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 02166 #endif /* TIM17 */ 02167 02168 #if defined(SAI1) 02169 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 02170 #endif /* SAI1 */ 02171 02172 #if defined(SAI2) 02173 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 02174 #endif /* SAI2 */ 02175 02176 #if defined(DFSDM1_Filter0) 02177 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U) 02178 #endif /* DFSDM1_Filter0 */ 02179 02180 #if defined(LTDC) 02181 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) 02182 #endif /* LTDC */ 02183 02184 #if defined(DSI) 02185 #define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U) 02186 #endif /* DSI */ 02187 02188 /** 02189 * @} 02190 */ 02191 02192 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 02193 * @brief Force or release AHB1 peripheral reset. 02194 * @{ 02195 */ 02196 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFUL) 02197 02198 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 02199 02200 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 02201 02202 #if defined(DMAMUX1) 02203 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 02204 #endif /* DMAMUX1 */ 02205 02206 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 02207 02208 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 02209 02210 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 02211 02212 #if defined(DMA2D) 02213 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 02214 #endif /* DMA2D */ 02215 02216 #if defined(GFXMMU) 02217 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 02218 #endif /* GFXMMU */ 02219 02220 02221 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000UL) 02222 02223 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 02224 02225 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 02226 02227 #if defined(DMAMUX1) 02228 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 02229 #endif /* DMAMUX1 */ 02230 02231 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 02232 02233 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 02234 02235 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 02236 02237 #if defined(DMA2D) 02238 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 02239 #endif /* DMA2D */ 02240 02241 #if defined(GFXMMU) 02242 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 02243 #endif /* GFXMMU */ 02244 02245 /** 02246 * @} 02247 */ 02248 02249 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 02250 * @brief Force or release AHB2 peripheral reset. 02251 * @{ 02252 */ 02253 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFUL) 02254 02255 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 02256 02257 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 02258 02259 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 02260 02261 #if defined(GPIOD) 02262 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 02263 #endif /* GPIOD */ 02264 02265 #if defined(GPIOE) 02266 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 02267 #endif /* GPIOE */ 02268 02269 #if defined(GPIOF) 02270 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 02271 #endif /* GPIOF */ 02272 02273 #if defined(GPIOG) 02274 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 02275 #endif /* GPIOG */ 02276 02277 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 02278 02279 #if defined(GPIOI) 02280 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 02281 #endif /* GPIOI */ 02282 02283 #if defined(USB_OTG_FS) 02284 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 02285 #endif /* USB_OTG_FS */ 02286 02287 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 02288 02289 #if defined(DCMI) 02290 #define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) 02291 #endif /* DCMI */ 02292 02293 #if defined(PKA) 02294 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 02295 #endif /* PKA */ 02296 02297 #if defined(AES) 02298 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 02299 #endif /* AES */ 02300 02301 #if defined(HASH) 02302 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 02303 #endif /* HASH */ 02304 02305 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 02306 02307 #if defined(OCTOSPIM) 02308 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) 02309 #endif /* OCTOSPIM */ 02310 02311 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) 02312 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 02313 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ 02314 02315 #if defined(SDMMC2) 02316 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST) 02317 #endif /* SDMMC2 */ 02318 02319 02320 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000UL) 02321 02322 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 02323 02324 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 02325 02326 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 02327 02328 #if defined(GPIOD) 02329 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 02330 #endif /* GPIOD */ 02331 02332 #if defined(GPIOE) 02333 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 02334 #endif /* GPIOE */ 02335 02336 #if defined(GPIOF) 02337 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 02338 #endif /* GPIOF */ 02339 02340 #if defined(GPIOG) 02341 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 02342 #endif /* GPIOG */ 02343 02344 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 02345 02346 #if defined(GPIOI) 02347 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 02348 #endif /* GPIOI */ 02349 02350 #if defined(USB_OTG_FS) 02351 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 02352 #endif /* USB_OTG_FS */ 02353 02354 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 02355 02356 #if defined(DCMI) 02357 #define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) 02358 #endif /* DCMI */ 02359 02360 #if defined(PKA) 02361 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 02362 #endif /* PKA */ 02363 02364 #if defined(AES) 02365 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 02366 #endif /* AES */ 02367 02368 #if defined(HASH) 02369 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 02370 #endif /* HASH */ 02371 02372 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 02373 02374 #if defined(OCTOSPIM) 02375 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) 02376 #endif /* OCTOSPIM */ 02377 02378 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) 02379 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 02380 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ 02381 02382 #if defined(SDMMC2) 02383 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST) 02384 #endif /* SDMMC2 */ 02385 02386 /** 02387 * @} 02388 */ 02389 02390 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 02391 * @brief Force or release AHB3 peripheral reset. 02392 * @{ 02393 */ 02394 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFUL) 02395 02396 #if defined(FMC_BANK1) 02397 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 02398 #endif /* FMC_BANK1 */ 02399 02400 #if defined(QUADSPI) 02401 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 02402 #endif /* QUADSPI */ 02403 02404 #if defined(OCTOSPI1) 02405 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 02406 #endif /* OCTOSPI1 */ 02407 02408 #if defined(OCTOSPI2) 02409 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) 02410 #endif /* OCTOSPI2 */ 02411 02412 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000UL) 02413 02414 #if defined(FMC_BANK1) 02415 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 02416 #endif /* FMC_BANK1 */ 02417 02418 #if defined(QUADSPI) 02419 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 02420 #endif /* QUADSPI */ 02421 02422 #if defined(OCTOSPI1) 02423 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 02424 #endif /* OCTOSPI1 */ 02425 02426 #if defined(OCTOSPI2) 02427 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) 02428 #endif /* OCTOSPI2 */ 02429 02430 /** 02431 * @} 02432 */ 02433 02434 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 02435 * @brief Force or release APB1 peripheral reset. 02436 * @{ 02437 */ 02438 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 02439 WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \ 02440 WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFUL); \ 02441 } while(0) 02442 02443 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 02444 02445 #if defined(TIM3) 02446 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 02447 #endif /* TIM3 */ 02448 02449 #if defined(TIM4) 02450 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 02451 #endif /* TIM4 */ 02452 02453 #if defined(TIM5) 02454 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 02455 #endif /* TIM5 */ 02456 02457 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 02458 02459 #if defined(TIM7) 02460 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 02461 #endif /* TIM7 */ 02462 02463 #if defined(LCD) 02464 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 02465 #endif /* LCD */ 02466 02467 #if defined(SPI2) 02468 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 02469 #endif /* SPI2 */ 02470 02471 #if defined(SPI3) 02472 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 02473 #endif /* SPI3 */ 02474 02475 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 02476 02477 #if defined(USART3) 02478 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 02479 #endif /* USART3 */ 02480 02481 #if defined(UART4) 02482 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 02483 #endif /* UART4 */ 02484 02485 #if defined(UART5) 02486 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 02487 #endif /* UART5 */ 02488 02489 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 02490 02491 #if defined(I2C2) 02492 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 02493 #endif /* I2C2 */ 02494 02495 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 02496 02497 #if defined(I2C4) 02498 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 02499 #endif /* I2C4 */ 02500 02501 #if defined(CRS) 02502 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 02503 #endif /* CRS */ 02504 02505 #if defined(CAN1) 02506 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 02507 #endif /* CAN1 */ 02508 02509 #if defined(CAN2) 02510 #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) 02511 #endif /* CAN2 */ 02512 02513 #if defined(USB) 02514 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 02515 #endif /* USB */ 02516 02517 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 02518 02519 #if defined(DAC1) 02520 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 02521 #endif /* DAC1 */ 02522 02523 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 02524 02525 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 02526 02527 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 02528 02529 #if defined(SWPMI1) 02530 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 02531 #endif /* SWPMI1 */ 02532 02533 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 02534 02535 02536 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 02537 WRITE_REG(RCC->APB1RSTR1, 0x00000000UL); \ 02538 WRITE_REG(RCC->APB1RSTR2, 0x00000000UL); \ 02539 } while(0) 02540 02541 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 02542 02543 #if defined(TIM3) 02544 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 02545 #endif /* TIM3 */ 02546 02547 #if defined(TIM4) 02548 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 02549 #endif /* TIM4 */ 02550 02551 #if defined(TIM5) 02552 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 02553 #endif /* TIM5 */ 02554 02555 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 02556 02557 #if defined(TIM7) 02558 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 02559 #endif /* TIM7 */ 02560 02561 #if defined(LCD) 02562 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 02563 #endif /* LCD */ 02564 02565 #if defined(SPI2) 02566 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 02567 #endif /* SPI2 */ 02568 02569 #if defined(SPI3) 02570 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 02571 #endif /* SPI3 */ 02572 02573 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 02574 02575 #if defined(USART3) 02576 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 02577 #endif /* USART3 */ 02578 02579 #if defined(UART4) 02580 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 02581 #endif /* UART4 */ 02582 02583 #if defined(UART5) 02584 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 02585 #endif /* UART5 */ 02586 02587 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 02588 02589 #if defined(I2C2) 02590 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 02591 #endif /* I2C2 */ 02592 02593 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 02594 02595 #if defined(I2C4) 02596 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 02597 #endif /* I2C4 */ 02598 02599 #if defined(CRS) 02600 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 02601 #endif /* CRS */ 02602 02603 #if defined(CAN1) 02604 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 02605 #endif /* CAN1 */ 02606 02607 #if defined(CAN2) 02608 #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) 02609 #endif /* CAN2 */ 02610 02611 #if defined(USB) 02612 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 02613 #endif /* USB */ 02614 02615 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 02616 02617 #if defined(DAC1) 02618 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 02619 #endif /* DAC1 */ 02620 02621 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 02622 02623 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 02624 02625 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 02626 02627 #if defined(SWPMI1) 02628 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 02629 #endif /* SWPMI1 */ 02630 02631 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 02632 02633 /** 02634 * @} 02635 */ 02636 02637 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 02638 * @brief Force or release APB2 peripheral reset. 02639 * @{ 02640 */ 02641 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFUL) 02642 02643 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 02644 02645 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 02646 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 02647 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 02648 02649 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 02650 02651 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 02652 02653 #if defined(TIM8) 02654 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 02655 #endif /* TIM8 */ 02656 02657 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 02658 02659 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 02660 02661 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 02662 02663 #if defined(TIM17) 02664 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 02665 #endif /* TIM17 */ 02666 02667 #if defined(SAI1) 02668 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 02669 #endif /* SAI1 */ 02670 02671 #if defined(SAI2) 02672 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 02673 #endif /* SAI2 */ 02674 02675 #if defined(DFSDM1_Filter0) 02676 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 02677 #endif /* DFSDM1_Filter0 */ 02678 02679 #if defined(LTDC) 02680 #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 02681 #endif /* LTDC */ 02682 02683 #if defined(DSI) 02684 #define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) 02685 #endif /* DSI */ 02686 02687 02688 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000UL) 02689 02690 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 02691 02692 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 02693 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 02694 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 02695 02696 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 02697 02698 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 02699 02700 #if defined(TIM8) 02701 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 02702 #endif /* TIM8 */ 02703 02704 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 02705 02706 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 02707 02708 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 02709 02710 #if defined(TIM17) 02711 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 02712 #endif /* TIM17 */ 02713 02714 #if defined(SAI1) 02715 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 02716 #endif /* SAI1 */ 02717 02718 #if defined(SAI2) 02719 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 02720 #endif /* SAI2 */ 02721 02722 #if defined(DFSDM1_Filter0) 02723 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 02724 #endif /* DFSDM1_Filter0 */ 02725 02726 #if defined(LTDC) 02727 #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 02728 #endif /* LTDC */ 02729 02730 #if defined(DSI) 02731 #define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) 02732 #endif /* DSI */ 02733 02734 /** 02735 * @} 02736 */ 02737 02738 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 02739 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 02740 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02741 * power consumption. 02742 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02743 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02744 * @{ 02745 */ 02746 02747 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 02748 02749 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 02750 02751 #if defined(DMAMUX1) 02752 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 02753 #endif /* DMAMUX1 */ 02754 02755 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 02756 02757 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 02758 02759 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 02760 02761 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 02762 02763 #if defined(DMA2D) 02764 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 02765 #endif /* DMA2D */ 02766 02767 #if defined(GFXMMU) 02768 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 02769 #endif /* GFXMMU */ 02770 02771 02772 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 02773 02774 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 02775 02776 #if defined(DMAMUX1) 02777 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 02778 #endif /* DMAMUX1 */ 02779 02780 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 02781 02782 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 02783 02784 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 02785 02786 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 02787 02788 #if defined(DMA2D) 02789 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 02790 #endif /* DMA2D */ 02791 02792 #if defined(GFXMMU) 02793 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 02794 #endif /* GFXMMU */ 02795 02796 /** 02797 * @} 02798 */ 02799 02800 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 02801 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 02802 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02803 * power consumption. 02804 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02805 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02806 * @{ 02807 */ 02808 02809 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 02810 02811 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 02812 02813 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 02814 02815 #if defined(GPIOD) 02816 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 02817 #endif /* GPIOD */ 02818 02819 #if defined(GPIOE) 02820 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 02821 #endif /* GPIOE */ 02822 02823 #if defined(GPIOF) 02824 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 02825 #endif /* GPIOF */ 02826 02827 #if defined(GPIOG) 02828 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 02829 #endif /* GPIOG */ 02830 02831 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 02832 02833 #if defined(GPIOI) 02834 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) 02835 #endif /* GPIOI */ 02836 02837 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 02838 02839 #if defined(SRAM3) 02840 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) 02841 #endif /* SRAM3 */ 02842 02843 #if defined(USB_OTG_FS) 02844 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 02845 #endif /* USB_OTG_FS */ 02846 02847 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 02848 02849 #if defined(DCMI) 02850 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) 02851 #endif /* DCMI */ 02852 02853 #if defined(PKA) 02854 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 02855 #endif /* PKA */ 02856 02857 #if defined(AES) 02858 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 02859 #endif /* AES */ 02860 02861 #if defined(HASH) 02862 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 02863 #endif /* HASH */ 02864 02865 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 02866 02867 #if defined(OCTOSPIM) 02868 #define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) 02869 #endif /* OCTOSPIM */ 02870 02871 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 02872 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 02873 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 02874 02875 #if defined(SDMMC2) 02876 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) 02877 #endif /* SDMMC2 */ 02878 02879 02880 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 02881 02882 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 02883 02884 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 02885 02886 #if defined(GPIOD) 02887 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 02888 #endif /* GPIOD */ 02889 02890 #if defined(GPIOE) 02891 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 02892 #endif /* GPIOE */ 02893 02894 #if defined(GPIOF) 02895 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 02896 #endif /* GPIOF */ 02897 02898 #if defined(GPIOG) 02899 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 02900 #endif /* GPIOG */ 02901 02902 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 02903 02904 #if defined(GPIOI) 02905 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) 02906 #endif /* GPIOI */ 02907 02908 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 02909 02910 #if defined(SRAM3) 02911 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) 02912 #endif /* SRAM3 */ 02913 02914 #if defined(USB_OTG_FS) 02915 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 02916 #endif /* USB_OTG_FS */ 02917 02918 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 02919 02920 #if defined(DCMI) 02921 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) 02922 #endif /* DCMI */ 02923 02924 #if defined(PKA) 02925 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 02926 #endif /* PKA */ 02927 02928 #if defined(AES) 02929 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 02930 #endif /* AES */ 02931 02932 #if defined(HASH) 02933 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 02934 #endif /* HASH */ 02935 02936 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 02937 02938 #if defined(OCTOSPIM) 02939 #define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) 02940 #endif /* OCTOSPIM */ 02941 02942 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 02943 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 02944 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 02945 02946 #if defined(SDMMC2) 02947 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) 02948 #endif /* SDMMC2 */ 02949 02950 /** 02951 * @} 02952 */ 02953 02954 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 02955 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 02956 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02957 * power consumption. 02958 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02959 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02960 * @{ 02961 */ 02962 02963 #if defined(QUADSPI) 02964 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 02965 #endif /* QUADSPI */ 02966 02967 #if defined(OCTOSPI1) 02968 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 02969 #endif /* OCTOSPI1 */ 02970 02971 #if defined(OCTOSPI2) 02972 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) 02973 #endif /* OCTOSPI2 */ 02974 02975 #if defined(FMC_BANK1) 02976 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 02977 #endif /* FMC_BANK1 */ 02978 02979 #if defined(QUADSPI) 02980 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 02981 #endif /* QUADSPI */ 02982 02983 #if defined(OCTOSPI1) 02984 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 02985 #endif /* OCTOSPI1 */ 02986 02987 #if defined(OCTOSPI2) 02988 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) 02989 #endif /* OCTOSPI2 */ 02990 02991 #if defined(FMC_BANK1) 02992 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 02993 #endif /* FMC_BANK1 */ 02994 02995 /** 02996 * @} 02997 */ 02998 02999 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 03000 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 03001 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03002 * power consumption. 03003 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03004 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03005 * @{ 03006 */ 03007 03008 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 03009 03010 #if defined(TIM3) 03011 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 03012 #endif /* TIM3 */ 03013 03014 #if defined(TIM4) 03015 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 03016 #endif /* TIM4 */ 03017 03018 #if defined(TIM5) 03019 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 03020 #endif /* TIM5 */ 03021 03022 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 03023 03024 #if defined(TIM7) 03025 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 03026 #endif /* TIM7 */ 03027 03028 #if defined(LCD) 03029 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 03030 #endif /* LCD */ 03031 03032 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 03033 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 03034 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 03035 03036 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 03037 03038 #if defined(SPI2) 03039 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 03040 #endif /* SPI2 */ 03041 03042 #if defined(SPI3) 03043 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 03044 #endif /* SPI3 */ 03045 03046 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 03047 03048 #if defined(USART3) 03049 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 03050 #endif /* USART3 */ 03051 03052 #if defined(UART4) 03053 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 03054 #endif /* UART4 */ 03055 03056 #if defined(UART5) 03057 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 03058 #endif /* UART5 */ 03059 03060 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 03061 03062 #if defined(I2C2) 03063 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 03064 #endif /* I2C2 */ 03065 03066 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 03067 03068 #if defined(I2C4) 03069 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 03070 #endif /* I2C4 */ 03071 03072 #if defined(CRS) 03073 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 03074 #endif /* CRS */ 03075 03076 #if defined(CAN1) 03077 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 03078 #endif /* CAN1 */ 03079 03080 #if defined(CAN2) 03081 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) 03082 #endif /* CAN2 */ 03083 03084 #if defined(USB) 03085 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 03086 #endif /* USB */ 03087 03088 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 03089 03090 #if defined(DAC1) 03091 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 03092 #endif /* DAC1 */ 03093 03094 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 03095 03096 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 03097 03098 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 03099 03100 #if defined(SWPMI1) 03101 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 03102 #endif /* SWPMI1 */ 03103 03104 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 03105 03106 03107 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 03108 03109 #if defined(TIM3) 03110 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 03111 #endif /* TIM3 */ 03112 03113 #if defined(TIM4) 03114 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 03115 #endif /* TIM4 */ 03116 03117 #if defined(TIM5) 03118 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 03119 #endif /* TIM5 */ 03120 03121 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 03122 03123 #if defined(TIM7) 03124 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 03125 #endif /* TIM7 */ 03126 03127 #if defined(LCD) 03128 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 03129 #endif /* LCD */ 03130 03131 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 03132 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 03133 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 03134 03135 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 03136 03137 #if defined(SPI2) 03138 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 03139 #endif /* SPI2 */ 03140 03141 #if defined(SPI3) 03142 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 03143 #endif /* SPI3 */ 03144 03145 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 03146 03147 #if defined(USART3) 03148 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 03149 #endif /* USART3 */ 03150 03151 #if defined(UART4) 03152 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 03153 #endif /* UART4 */ 03154 03155 #if defined(UART5) 03156 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 03157 #endif /* UART5 */ 03158 03159 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 03160 03161 #if defined(I2C2) 03162 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 03163 #endif /* I2C2 */ 03164 03165 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 03166 03167 #if defined(I2C4) 03168 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 03169 #endif /* I2C4 */ 03170 03171 #if defined(CRS) 03172 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 03173 #endif /* CRS */ 03174 03175 #if defined(CAN1) 03176 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 03177 #endif /* CAN1 */ 03178 03179 #if defined(CAN2) 03180 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) 03181 #endif /* CAN2 */ 03182 03183 #if defined(USB) 03184 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 03185 #endif /* USB */ 03186 03187 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 03188 03189 #if defined(DAC1) 03190 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 03191 #endif /* DAC1 */ 03192 03193 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 03194 03195 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 03196 03197 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 03198 03199 #if defined(SWPMI1) 03200 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 03201 #endif /* SWPMI1 */ 03202 03203 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 03204 03205 /** 03206 * @} 03207 */ 03208 03209 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 03210 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 03211 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03212 * power consumption. 03213 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03214 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03215 * @{ 03216 */ 03217 03218 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 03219 03220 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 03221 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 03222 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 03223 03224 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 03225 03226 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 03227 03228 #if defined(TIM8) 03229 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 03230 #endif /* TIM8 */ 03231 03232 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 03233 03234 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 03235 03236 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 03237 03238 #if defined(TIM17) 03239 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 03240 #endif /* TIM17 */ 03241 03242 #if defined(SAI1) 03243 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 03244 #endif /* SAI1 */ 03245 03246 #if defined(SAI2) 03247 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 03248 #endif /* SAI2 */ 03249 03250 #if defined(DFSDM1_Filter0) 03251 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 03252 #endif /* DFSDM1_Filter0 */ 03253 03254 #if defined(LTDC) 03255 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 03256 #endif /* LTDC */ 03257 03258 #if defined(DSI) 03259 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) 03260 #endif /* DSI */ 03261 03262 03263 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 03264 03265 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 03266 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 03267 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 03268 03269 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 03270 03271 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 03272 03273 #if defined(TIM8) 03274 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 03275 #endif /* TIM8 */ 03276 03277 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 03278 03279 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 03280 03281 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 03282 03283 #if defined(TIM17) 03284 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 03285 #endif /* TIM17 */ 03286 03287 #if defined(SAI1) 03288 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 03289 #endif /* SAI1 */ 03290 03291 #if defined(SAI2) 03292 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 03293 #endif /* SAI2 */ 03294 03295 #if defined(DFSDM1_Filter0) 03296 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 03297 #endif /* DFSDM1_Filter0 */ 03298 03299 #if defined(LTDC) 03300 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 03301 #endif /* LTDC */ 03302 03303 #if defined(DSI) 03304 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) 03305 #endif /* DSI */ 03306 03307 /** 03308 * @} 03309 */ 03310 03311 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 03312 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 03313 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03314 * power consumption. 03315 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03316 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03317 * @{ 03318 */ 03319 03320 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) 03321 03322 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) 03323 03324 #if defined(DMAMUX1) 03325 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) 03326 #endif /* DMAMUX1 */ 03327 03328 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) 03329 03330 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) 03331 03332 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) 03333 03334 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) 03335 03336 #if defined(DMA2D) 03337 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U) 03338 #endif /* DMA2D */ 03339 03340 #if defined(GFXMMU) 03341 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U) 03342 #endif /* GFXMMU */ 03343 03344 03345 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) 03346 03347 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) 03348 03349 #if defined(DMAMUX1) 03350 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) 03351 #endif /* DMAMUX1 */ 03352 03353 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) 03354 03355 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) 03356 03357 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) 03358 03359 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U) 03360 03361 #if defined(DMA2D) 03362 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U) 03363 #endif /* DMA2D */ 03364 03365 #if defined(GFXMMU) 03366 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U) 03367 #endif /* GFXMMU */ 03368 03369 /** 03370 * @} 03371 */ 03372 03373 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 03374 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 03375 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03376 * power consumption. 03377 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03378 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03379 * @{ 03380 */ 03381 03382 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) 03383 03384 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) 03385 03386 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) 03387 03388 #if defined(GPIOD) 03389 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) 03390 #endif /* GPIOD */ 03391 03392 #if defined(GPIOE) 03393 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) 03394 #endif /* GPIOE */ 03395 03396 #if defined(GPIOF) 03397 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) 03398 #endif /* GPIOF */ 03399 03400 #if defined(GPIOG) 03401 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) 03402 #endif /* GPIOG */ 03403 03404 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) 03405 03406 #if defined(GPIOI) 03407 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U) 03408 #endif /* GPIOI */ 03409 03410 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) 03411 03412 #if defined(SRAM3) 03413 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U) 03414 #endif /* SRAM3 */ 03415 03416 #if defined(USB_OTG_FS) 03417 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U) 03418 #endif /* USB_OTG_FS */ 03419 03420 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U) 03421 03422 #if defined(DCMI) 03423 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U) 03424 #endif /* DCMI */ 03425 03426 #if defined(PKA) 03427 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) != 0U) 03428 #endif /* PKA */ 03429 03430 #if defined(AES) 03431 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) 03432 #endif /* AES */ 03433 03434 #if defined(HASH) 03435 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) 03436 #endif /* HASH */ 03437 03438 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) 03439 03440 #if defined(OCTOSPIM) 03441 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U) 03442 #endif /* OCTOSPIM */ 03443 03444 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 03445 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U) 03446 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 03447 03448 #if defined(SDMMC2) 03449 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) != 0U) 03450 #endif /* SDMMC2 */ 03451 03452 03453 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) 03454 03455 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) 03456 03457 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) 03458 03459 #if defined(GPIOD) 03460 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) 03461 #endif /* GPIOD */ 03462 03463 #if defined(GPIOE) 03464 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) 03465 #endif /* GPIOE */ 03466 03467 #if defined(GPIOF) 03468 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) 03469 #endif /* GPIOF */ 03470 03471 #if defined(GPIOG) 03472 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) 03473 #endif /* GPIOG */ 03474 03475 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U) 03476 03477 #if defined(GPIOI) 03478 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U) 03479 #endif /* GPIOI */ 03480 03481 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) 03482 03483 #if defined(SRAM3) 03484 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U) 03485 #endif /* SRAM3 */ 03486 03487 #if defined(USB_OTG_FS) 03488 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U) 03489 #endif /* USB_OTG_FS */ 03490 03491 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U) 03492 03493 #if defined(DCMI) 03494 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U) 03495 #endif /* DCMI */ 03496 03497 #if defined(PKA) 03498 #define __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) == 0U) 03499 #endif /* PKA */ 03500 03501 #if defined(AES) 03502 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) 03503 #endif /* AES */ 03504 03505 #if defined(HASH) 03506 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U) 03507 #endif /* HASH */ 03508 03509 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) 03510 03511 #if defined(OCTOSPIM) 03512 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U) 03513 #endif /* OCTOSPIM */ 03514 03515 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 03516 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U) 03517 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 03518 03519 #if defined(SDMMC2) 03520 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) == 0U) 03521 #endif /* SDMMC2 */ 03522 03523 /** 03524 * @} 03525 */ 03526 03527 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 03528 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 03529 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03530 * power consumption. 03531 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03532 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03533 * @{ 03534 */ 03535 03536 #if defined(QUADSPI) 03537 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U) 03538 #endif /* QUADSPI */ 03539 03540 #if defined(OCTOSPI1) 03541 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U) 03542 #endif /* OCTOSPI1 */ 03543 03544 #if defined(OCTOSPI2) 03545 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U) 03546 #endif /* OCTOSPI2 */ 03547 03548 #if defined(FMC_BANK1) 03549 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) 03550 #endif /* FMC_BANK1 */ 03551 03552 03553 #if defined(QUADSPI) 03554 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U) 03555 #endif /* QUADSPI */ 03556 03557 #if defined(OCTOSPI1) 03558 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U) 03559 #endif /* OCTOSPI1 */ 03560 03561 #if defined(OCTOSPI2) 03562 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U) 03563 #endif /* OCTOSPI2 */ 03564 03565 #if defined(FMC_BANK1) 03566 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) 03567 #endif /* FMC_BANK1 */ 03568 03569 /** 03570 * @} 03571 */ 03572 03573 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 03574 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 03575 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03576 * power consumption. 03577 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03578 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03579 * @{ 03580 */ 03581 03582 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) 03583 03584 #if defined(TIM3) 03585 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) 03586 #endif /* TIM3 */ 03587 03588 #if defined(TIM4) 03589 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) 03590 #endif /* TIM4 */ 03591 03592 #if defined(TIM5) 03593 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) 03594 #endif /* TIM5 */ 03595 03596 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) 03597 03598 #if defined(TIM7) 03599 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) 03600 #endif /* TIM7 */ 03601 03602 #if defined(LCD) 03603 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U) 03604 #endif /* LCD */ 03605 03606 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 03607 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) 03608 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 03609 03610 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) 03611 03612 #if defined(SPI2) 03613 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) 03614 #endif /* SPI2 */ 03615 03616 #if defined(SPI3) 03617 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) 03618 #endif /* SPI3 */ 03619 03620 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) 03621 03622 #if defined(USART3) 03623 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) 03624 #endif /* USART3 */ 03625 03626 #if defined(UART4) 03627 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) 03628 #endif /* UART4 */ 03629 03630 #if defined(UART5) 03631 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) 03632 #endif /* UART5 */ 03633 03634 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) 03635 03636 #if defined(I2C2) 03637 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) 03638 #endif /* I2C2 */ 03639 03640 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) 03641 03642 #if defined(I2C4) 03643 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) 03644 #endif /* I2C4 */ 03645 03646 #if defined(CRS) 03647 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) 03648 #endif /* CRS */ 03649 03650 #if defined(CAN1) 03651 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U) 03652 #endif /* CAN1 */ 03653 03654 #if defined(CAN2) 03655 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U) 03656 #endif /* CAN2 */ 03657 03658 #if defined(USB) 03659 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U) 03660 #endif /* USB */ 03661 03662 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) 03663 03664 #if defined(DAC1) 03665 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U) 03666 #endif /* DAC1 */ 03667 03668 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U) 03669 03670 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) 03671 03672 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) 03673 03674 #if defined(SWPMI1) 03675 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U) 03676 #endif /* SWPMI1 */ 03677 03678 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) 03679 03680 03681 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) 03682 03683 #if defined(TIM3) 03684 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) 03685 #endif /* TIM3 */ 03686 03687 #if defined(TIM4) 03688 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) 03689 #endif /* TIM4 */ 03690 03691 #if defined(TIM5) 03692 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) 03693 #endif /* TIM5 */ 03694 03695 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) 03696 03697 #if defined(TIM7) 03698 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) 03699 #endif /* TIM7 */ 03700 03701 #if defined(LCD) 03702 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U) 03703 #endif /* LCD */ 03704 03705 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 03706 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) 03707 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 03708 03709 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) 03710 03711 #if defined(SPI2) 03712 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) 03713 #endif /* SPI2 */ 03714 03715 #if defined(SPI3) 03716 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) 03717 #endif /* SPI3 */ 03718 03719 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) 03720 03721 #if defined(USART3) 03722 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) 03723 #endif /* USART3 */ 03724 03725 #if defined(UART4) 03726 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) 03727 #endif /* UART4 */ 03728 03729 #if defined(UART5) 03730 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) 03731 #endif /* UART5 */ 03732 03733 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) 03734 03735 #if defined(I2C2) 03736 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) 03737 #endif /* I2C2 */ 03738 03739 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) 03740 03741 #if defined(I2C4) 03742 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) 03743 #endif /* I2C4 */ 03744 03745 #if defined(CRS) 03746 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) 03747 #endif /* CRS */ 03748 03749 #if defined(CAN1) 03750 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U) 03751 #endif /* CAN1 */ 03752 03753 #if defined(CAN2) 03754 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U) 03755 #endif /* CAN2 */ 03756 03757 #if defined(USB) 03758 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U) 03759 #endif /* USB */ 03760 03761 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) 03762 03763 #if defined(DAC1) 03764 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U) 03765 #endif /* DAC1 */ 03766 03767 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U) 03768 03769 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) 03770 03771 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) 03772 03773 #if defined(SWPMI1) 03774 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U) 03775 #endif /* SWPMI1 */ 03776 03777 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U) 03778 03779 /** 03780 * @} 03781 */ 03782 03783 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 03784 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 03785 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03786 * power consumption. 03787 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03788 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03789 * @{ 03790 */ 03791 03792 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) 03793 03794 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 03795 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U) 03796 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 03797 03798 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) 03799 03800 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) 03801 03802 #if defined(TIM8) 03803 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) 03804 #endif /* TIM8 */ 03805 03806 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) 03807 03808 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) 03809 03810 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) 03811 03812 #if defined(TIM17) 03813 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) 03814 #endif /* TIM17 */ 03815 03816 #if defined(SAI1) 03817 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) 03818 #endif /* SAI1 */ 03819 03820 #if defined(SAI2) 03821 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U) 03822 #endif /* SAI2 */ 03823 03824 #if defined(DFSDM1_Filter0) 03825 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U) 03826 #endif /* DFSDM1_Filter0 */ 03827 03828 #if defined(LTDC) 03829 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U) 03830 #endif /* LTDC */ 03831 03832 #if defined(DSI) 03833 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U) 03834 #endif /* DSI */ 03835 03836 03837 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) 03838 03839 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 03840 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U) 03841 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 03842 03843 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) 03844 03845 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) 03846 03847 #if defined(TIM8) 03848 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) 03849 #endif /* TIM8 */ 03850 03851 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) 03852 03853 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) 03854 03855 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) 03856 03857 #if defined(TIM17) 03858 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) 03859 #endif /* TIM17 */ 03860 03861 #if defined(SAI1) 03862 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) 03863 #endif /* SAI1 */ 03864 03865 #if defined(SAI2) 03866 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U) 03867 #endif /* SAI2 */ 03868 03869 #if defined(DFSDM1_Filter0) 03870 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U) 03871 #endif /* DFSDM1_Filter0 */ 03872 03873 #if defined(LTDC) 03874 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U) 03875 #endif /* LTDC */ 03876 03877 #if defined(DSI) 03878 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U) 03879 #endif /* DSI */ 03880 03881 /** 03882 * @} 03883 */ 03884 03885 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 03886 * @{ 03887 */ 03888 03889 /** @brief Macros to force or release the Backup domain reset. 03890 * @note This function resets the RTC peripheral (including the backup registers) 03891 * and the RTC clock source selection in RCC_CSR register. 03892 * @note The BKPSRAM is not affected by this reset. 03893 * @retval None 03894 */ 03895 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 03896 03897 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 03898 03899 /** 03900 * @} 03901 */ 03902 03903 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 03904 * @{ 03905 */ 03906 03907 /** @brief Macros to enable or disable the RTC clock. 03908 * @note As the RTC is in the Backup domain and write access is denied to 03909 * this domain after reset, you have to enable write access using 03910 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 03911 * (to be done once after reset). 03912 * @note These macros must be used after the RTC clock source was selected. 03913 * @retval None 03914 */ 03915 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 03916 03917 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 03918 03919 /** 03920 * @} 03921 */ 03922 03923 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 03924 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 03925 * It is used (enabled by hardware) as system clock source after startup 03926 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 03927 * of the HSE used directly or indirectly as system clock (if the Clock 03928 * Security System CSS is enabled). 03929 * @note HSI can not be stopped if it is used as system clock source. In this case, 03930 * you have to select another source of the system clock then stop the HSI. 03931 * @note After enabling the HSI, the application software should wait on HSIRDY 03932 * flag to be set indicating that HSI clock is stable and can be used as 03933 * system clock source. 03934 * This parameter can be: ENABLE or DISABLE. 03935 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 03936 * clock cycles. 03937 * @retval None 03938 */ 03939 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 03940 03941 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 03942 03943 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 03944 * @note The calibration is used to compensate for the variations in voltage 03945 * and temperature that influence the frequency of the internal HSI RC. 03946 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 03947 * (default is RCC_HSICALIBRATION_DEFAULT). 03948 * This parameter must be a number between 0 and 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x 03949 * or between 0 and 127 on other devices. 03950 * @retval None 03951 */ 03952 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 03953 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 03954 03955 /** 03956 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 03957 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 03958 * @note The enable of this function has not effect on the HSION bit. 03959 * This parameter can be: ENABLE or DISABLE. 03960 * @retval None 03961 */ 03962 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) 03963 03964 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) 03965 03966 /** 03967 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 03968 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 03969 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 03970 * speed because of the HSI startup time. 03971 * @note The enable of this function has not effect on the HSION bit. 03972 * This parameter can be: ENABLE or DISABLE. 03973 * @retval None 03974 */ 03975 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 03976 03977 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 03978 03979 /** 03980 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 03981 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 03982 * It is used (enabled by hardware) as system clock source after 03983 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 03984 * of failure of the HSE used directly or indirectly as system clock 03985 * (if the Clock Security System CSS is enabled). 03986 * @note MSI can not be stopped if it is used as system clock source. 03987 * In this case, you have to select another source of the system 03988 * clock then stop the MSI. 03989 * @note After enabling the MSI, the application software should wait on 03990 * MSIRDY flag to be set indicating that MSI clock is stable and can 03991 * be used as system clock source. 03992 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 03993 * clock cycles. 03994 * @retval None 03995 */ 03996 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 03997 03998 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 03999 04000 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. 04001 * @note The calibration is used to compensate for the variations in voltage 04002 * and temperature that influence the frequency of the internal MSI RC. 04003 * Refer to the Application Note AN3300 for more details on how to 04004 * calibrate the MSI. 04005 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 04006 * (default is RCC_MSICALIBRATION_DEFAULT). 04007 * This parameter must be a number between 0 and 255. 04008 * @retval None 04009 */ 04010 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 04011 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) 04012 04013 /** 04014 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 04015 * @note After restart from Reset , the MSI clock is around 4 MHz. 04016 * After stop the startup clock can be MSI (at any of its possible 04017 * frequencies, the one that was used before entering stop mode) or HSI. 04018 * After Standby its frequency can be selected between 4 possible values 04019 * (1, 2, 4 or 8 MHz). 04020 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 04021 * (MSIRDY=1). 04022 * @note The MSI clock range after reset can be modified on the fly. 04023 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 04024 * This parameter must be one of the following values: 04025 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 04026 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 04027 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 04028 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 04029 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 04030 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 04031 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 04032 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 04033 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 04034 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 04035 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 04036 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 04037 * @retval None 04038 */ 04039 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 04040 do { \ 04041 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ 04042 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ 04043 } while(0) 04044 04045 /** 04046 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 04047 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 04048 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 04049 * This parameter must be one of the following values: 04050 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 04051 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 04052 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 04053 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 04054 * @retval None 04055 */ 04056 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ 04057 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) 04058 04059 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 04060 * @retval MSI clock range. 04061 * This parameter must be one of the following values: 04062 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 04063 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 04064 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 04065 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 04066 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 04067 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 04068 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 04069 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 04070 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 04071 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 04072 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 04073 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 04074 */ 04075 #define __HAL_RCC_GET_MSI_RANGE() \ 04076 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ 04077 READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ 04078 (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U)) 04079 04080 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 04081 * @note After enabling the LSI, the application software should wait on 04082 * LSIRDY flag to be set indicating that LSI clock is stable and can 04083 * be used to clock the IWDG and/or the RTC. 04084 * @note LSI can not be disabled if the IWDG is running. 04085 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 04086 * clock cycles. 04087 * @retval None 04088 */ 04089 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 04090 04091 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 04092 04093 /** 04094 * @brief Macro to configure the External High Speed oscillator (HSE). 04095 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 04096 * supported by this macro. User should request a transition to HSE Off 04097 * first and then HSE On or HSE Bypass. 04098 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 04099 * software should wait on HSERDY flag to be set indicating that HSE clock 04100 * is stable and can be used to clock the PLL and/or system clock. 04101 * @note HSE state can not be changed if it is used directly or through the 04102 * PLL as system clock. In this case, you have to select another source 04103 * of the system clock then change the HSE state (ex. disable it). 04104 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 04105 * @note This function reset the CSSON bit, so if the clock security system(CSS) 04106 * was previously enabled you have to enable it again after calling this 04107 * function. 04108 * @param __STATE__ specifies the new state of the HSE. 04109 * This parameter can be one of the following values: 04110 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 04111 * 6 HSE oscillator clock cycles. 04112 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 04113 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 04114 * @retval None 04115 */ 04116 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 04117 do { \ 04118 if((__STATE__) == RCC_HSE_ON) \ 04119 { \ 04120 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 04121 } \ 04122 else if((__STATE__) == RCC_HSE_BYPASS) \ 04123 { \ 04124 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 04125 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 04126 } \ 04127 else \ 04128 { \ 04129 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 04130 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 04131 } \ 04132 } while(0) 04133 04134 /** 04135 * @brief Macro to configure the External Low Speed oscillator (LSE). 04136 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 04137 * supported by this macro. User should request a transition to LSE Off 04138 * first and then LSE On or LSE Bypass. 04139 * @note As the LSE is in the Backup domain and write access is denied to 04140 * this domain after reset, you have to enable write access using 04141 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 04142 * (to be done once after reset). 04143 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 04144 * software should wait on LSERDY flag to be set indicating that LSE clock 04145 * is stable and can be used to clock the RTC. 04146 * @param __STATE__ specifies the new state of the LSE. 04147 * This parameter can be one of the following values: 04148 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 04149 * 6 LSE oscillator clock cycles. 04150 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 04151 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 04152 * @retval None 04153 */ 04154 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 04155 do { \ 04156 if((__STATE__) == RCC_LSE_ON) \ 04157 { \ 04158 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 04159 } \ 04160 else if((__STATE__) == RCC_LSE_BYPASS) \ 04161 { \ 04162 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 04163 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 04164 } \ 04165 else \ 04166 { \ 04167 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 04168 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 04169 } \ 04170 } while(0) 04171 04172 #if defined(RCC_HSI48_SUPPORT) 04173 04174 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 04175 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 04176 * @note After enabling the HSI48, the application software should wait on HSI48RDY 04177 * flag to be set indicating that HSI48 clock is stable. 04178 * This parameter can be: ENABLE or DISABLE. 04179 * @retval None 04180 */ 04181 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 04182 04183 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 04184 04185 #endif /* RCC_HSI48_SUPPORT */ 04186 04187 /** @brief Macros to configure the RTC clock (RTCCLK). 04188 * @note As the RTC clock configuration bits are in the Backup domain and write 04189 * access is denied to this domain after reset, you have to enable write 04190 * access using the Power Backup Access macro before to configure 04191 * the RTC clock source (to be done once after reset). 04192 * @note Once the RTC clock is configured it cannot be changed unless the 04193 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 04194 * a Power On Reset (POR). 04195 * 04196 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 04197 * This parameter can be one of the following values: 04198 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 04199 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 04200 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 04201 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 04202 * 04203 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 04204 * work in STOP and STANDBY modes, and can be used as wakeup source. 04205 * However, when the HSE clock is used as RTC clock source, the RTC 04206 * cannot be used in STOP and STANDBY modes. 04207 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 04208 * RTC clock source). 04209 * @retval None 04210 */ 04211 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 04212 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 04213 04214 04215 /** @brief Macro to get the RTC clock source. 04216 * @retval The returned value can be one of the following: 04217 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 04218 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 04219 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 04220 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 04221 */ 04222 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 04223 04224 /** @brief Macros to enable or disable the main PLL. 04225 * @note After enabling the main PLL, the application software should wait on 04226 * PLLRDY flag to be set indicating that PLL clock is stable and can 04227 * be used as system clock source. 04228 * @note The main PLL can not be disabled if it is used as system clock source 04229 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 04230 * @retval None 04231 */ 04232 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 04233 04234 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 04235 04236 /** @brief Macro to configure the PLL clock source. 04237 * @note This function must be used only when the main PLL is disabled. 04238 * @param __PLLSOURCE__ specifies the PLL entry clock source. 04239 * This parameter can be one of the following values: 04240 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 04241 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 04242 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 04243 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 04244 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 04245 * @retval None 04246 * 04247 */ 04248 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 04249 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 04250 04251 /** @brief Macro to configure the PLL source division factor M. 04252 * @note This function must be used only when the main PLL is disabled. 04253 * @param __PLLM__ specifies the division factor for PLL VCO input clock 04254 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 04255 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. 04256 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 04257 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 04258 * of 16 MHz to limit PLL jitter. 04259 * @retval None 04260 * 04261 */ 04262 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 04263 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) 04264 04265 /** 04266 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 04267 * @note This function must be used only when the main PLL is disabled. 04268 * 04269 * @param __PLLSOURCE__ specifies the PLL entry clock source. 04270 * This parameter can be one of the following values: 04271 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 04272 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 04273 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 04274 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 04275 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 04276 * 04277 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 04278 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 04279 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. 04280 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 04281 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 04282 * of 16 MHz to limit PLL jitter. 04283 * 04284 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 04285 * This parameter must be a number between 8 and 86. 04286 * @note You have to set the PLLN parameter correctly to ensure that the VCO 04287 * output frequency is between 64 and 344 MHz. 04288 * 04289 * @param __PLLP__ specifies the division factor for SAI clock when SAI available on device. 04290 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x 04291 * else (2 to 31). 04292 * 04293 * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. 04294 * This parameter must be in the range (2, 4, 6 or 8). 04295 * @note If the USB OTG FS is used in your application, you have to set the 04296 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 04297 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work 04298 * correctly. 04299 * @param __PLLR__ specifies the division factor for the main system clock. 04300 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. 04301 * This parameter must be in the range (2, 4, 6 or 8). 04302 * @retval None 04303 */ 04304 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 04305 04306 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 04307 MODIFY_REG(RCC->PLLCFGR, \ 04308 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 04309 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \ 04310 ((__PLLSOURCE__) | \ 04311 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 04312 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 04313 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 04314 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ 04315 ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) 04316 04317 #elif defined(RCC_PLLP_SUPPORT) 04318 04319 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 04320 MODIFY_REG(RCC->PLLCFGR, \ 04321 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 04322 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \ 04323 ((__PLLSOURCE__) | \ 04324 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 04325 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 04326 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 04327 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ 04328 (((__PLLP__) >> 4U) << RCC_PLLCFGR_PLLP_Pos))) 04329 04330 #else 04331 04332 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \ 04333 MODIFY_REG(RCC->PLLCFGR, \ 04334 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 04335 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \ 04336 ((__PLLSOURCE__) | \ 04337 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 04338 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 04339 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 04340 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) 04341 04342 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 04343 04344 /** @brief Macro to get the oscillator used as PLL clock source. 04345 * @retval The oscillator used as PLL clock source. The returned value can be one 04346 * of the following: 04347 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 04348 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 04349 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 04350 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 04351 */ 04352 #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) 04353 04354 /** 04355 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 04356 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime 04357 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 04358 * be stopped if used as System Clock. 04359 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 04360 * This parameter can be one or a combination of the following values: 04361 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 04362 * high-quality audio performance on SAI interface in case. 04363 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 04364 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 04365 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 04366 * @retval None 04367 */ 04368 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 04369 04370 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 04371 04372 /** 04373 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 04374 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 04375 * This parameter can be one of the following values: 04376 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 04377 * high-quality audio performance on SAI interface in case. 04378 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 04379 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 04380 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 04381 * @retval SET / RESET 04382 */ 04383 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 04384 04385 /** 04386 * @brief Macro to configure the system clock source. 04387 * @param __SYSCLKSOURCE__ specifies the system clock source. 04388 * This parameter can be one of the following values: 04389 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 04390 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 04391 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 04392 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 04393 * @retval None 04394 */ 04395 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 04396 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 04397 04398 /** @brief Macro to get the clock source used as system clock. 04399 * @retval The clock source used as system clock. The returned value can be one 04400 * of the following: 04401 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. 04402 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 04403 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 04404 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 04405 */ 04406 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) 04407 04408 /** 04409 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 04410 * @note As the LSE is in the Backup domain and write access is denied to 04411 * this domain after reset, you have to enable write access using 04412 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 04413 * (to be done once after reset). 04414 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 04415 * This parameter can be one of the following values: 04416 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 04417 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 04418 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 04419 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 04420 * @retval None 04421 */ 04422 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 04423 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) 04424 04425 /** 04426 * @brief Macro to configure the wake up from stop clock. 04427 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 04428 * This parameter can be one of the following values: 04429 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 04430 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 04431 * @retval None 04432 */ 04433 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 04434 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) 04435 04436 04437 /** @brief Macro to configure the MCO clock. 04438 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 04439 * This parameter can be one of the following values: 04440 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 04441 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 04442 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 04443 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 04444 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 04445 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 04446 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 04447 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 04448 @if STM32L443xx 04449 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 04450 @endif 04451 @if STM32L4A6xx 04452 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 04453 @endif 04454 * @param __MCODIV__ specifies the MCO clock prescaler. 04455 * This parameter can be one of the following values: 04456 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 04457 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 04458 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 04459 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 04460 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 04461 */ 04462 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 04463 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 04464 04465 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 04466 * @brief macros to manage the specified RCC Flags and interrupts. 04467 * @{ 04468 */ 04469 04470 /** @brief Enable RCC interrupt(s). 04471 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. 04472 * This parameter can be any combination of the following values: 04473 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 04474 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 04475 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 04476 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 04477 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 04478 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 04479 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 04480 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 04481 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 04482 @if STM32L443xx 04483 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04484 @endif 04485 @if STM32L4A6xx 04486 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04487 @endif 04488 * @retval None 04489 */ 04490 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 04491 04492 /** @brief Disable RCC interrupt(s). 04493 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. 04494 * This parameter can be any combination of the following values: 04495 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 04496 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 04497 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 04498 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 04499 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 04500 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 04501 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 04502 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 04503 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 04504 @if STM32L443xx 04505 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04506 @endif 04507 @if STM32L4A6xx 04508 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04509 @endif 04510 * @retval None 04511 */ 04512 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 04513 04514 /** @brief Clear the RCC's interrupt pending bits. 04515 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 04516 * This parameter can be any combination of the following values: 04517 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 04518 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 04519 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 04520 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 04521 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 04522 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 04523 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 04524 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 04525 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 04526 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 04527 @if STM32L443xx 04528 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04529 @endif 04530 @if STM32L4A6xx 04531 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04532 @endif 04533 * @retval None 04534 */ 04535 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 04536 04537 /** @brief Check whether the RCC interrupt has occurred or not. 04538 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 04539 * This parameter can be one of the following values: 04540 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 04541 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 04542 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 04543 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 04544 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 04545 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 04546 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 04547 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 04548 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 04549 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 04550 @if STM32L443xx 04551 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04552 @endif 04553 @if STM32L4A6xx 04554 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04555 @endif 04556 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 04557 */ 04558 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) 04559 04560 /** @brief Set RMVF bit to clear the reset flags. 04561 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 04562 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 04563 * @retval None 04564 */ 04565 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) 04566 04567 /** @brief Check whether the selected RCC flag is set or not. 04568 * @param __FLAG__ specifies the flag to check. 04569 * This parameter can be one of the following values: 04570 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 04571 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 04572 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 04573 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 04574 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready for devices with PLLSAI1 04575 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 04576 @if STM32L443xx 04577 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 04578 @endif 04579 @if STM32L4A6xx 04580 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 04581 @endif 04582 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 04583 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 04584 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 04585 * @arg @ref RCC_FLAG_BORRST BOR reset 04586 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 04587 * @arg @ref RCC_FLAG_PINRST Pin reset 04588 * @arg @ref RCC_FLAG_FWRST FIREWALL reset 04589 * @arg @ref RCC_FLAG_SFTRST Software reset 04590 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 04591 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 04592 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 04593 * @retval The new state of __FLAG__ (TRUE or FALSE). 04594 */ 04595 #if defined(RCC_HSI48_SUPPORT) 04596 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 04597 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ 04598 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 04599 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 04600 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 04601 #else 04602 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 04603 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 04604 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ 04605 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 04606 #endif /* RCC_HSI48_SUPPORT */ 04607 04608 /** 04609 * @} 04610 */ 04611 04612 /** 04613 * @} 04614 */ 04615 04616 /* Private constants ---------------------------------------------------------*/ 04617 /** @defgroup RCC_Private_Constants RCC Private Constants 04618 * @{ 04619 */ 04620 /* Defines used for Flags */ 04621 #define CR_REG_INDEX 1U 04622 #define BDCR_REG_INDEX 2U 04623 #define CSR_REG_INDEX 3U 04624 #if defined(RCC_HSI48_SUPPORT) 04625 #define CRRCR_REG_INDEX 4U 04626 #endif /* RCC_HSI48_SUPPORT */ 04627 04628 #define RCC_FLAG_MASK 0x1FU 04629 04630 /* Defines Oscillator Masks */ 04631 #if defined(RCC_HSI48_SUPPORT) 04632 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ 04633 #else 04634 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ 04635 #endif /* RCC_HSI48_SUPPORT */ 04636 04637 /** @defgroup RCC_Reset_Flag Reset Flag 04638 * @{ 04639 */ 04640 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 04641 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 04642 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 04643 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 04644 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 04645 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 04646 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 04647 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 04648 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 04649 RCC_RESET_FLAG_LPWR) 04650 /** 04651 * @} 04652 */ 04653 04654 /** 04655 * @} 04656 */ 04657 04658 /* Private macros ------------------------------------------------------------*/ 04659 /** @addtogroup RCC_Private_Macros 04660 * @{ 04661 */ 04662 04663 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 04664 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) 04665 04666 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 04667 ((__HSE__) == RCC_HSE_BYPASS)) 04668 04669 #if defined(RCC_BDCR_LSESYSDIS) 04670 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ 04671 ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS)) 04672 #else 04673 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 04674 ((__LSE__) == RCC_LSE_BYPASS)) 04675 #endif /* RCC_BDCR_LSESYSDIS */ 04676 04677 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 04678 04679 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) 04680 04681 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 04682 04683 #if defined(RCC_CSR_LSIPREDIV) 04684 #define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) 04685 #endif /* RCC_CSR_LSIPREDIV */ 04686 04687 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 04688 04689 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) 04690 04691 #if defined(RCC_HSI48_SUPPORT) 04692 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 04693 #endif /* RCC_HSI48_SUPPORT */ 04694 04695 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 04696 ((__PLL__) == RCC_PLL_ON)) 04697 04698 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 04699 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 04700 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 04701 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 04702 04703 #if defined(RCC_PLLM_DIV_1_16_SUPPORT) 04704 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 04705 #else 04706 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 04707 #endif /*RCC_PLLM_DIV_1_16_SUPPORT */ 04708 04709 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 04710 04711 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 04712 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 04713 #else 04714 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 04715 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */ 04716 04717 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 04718 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 04719 04720 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 04721 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 04722 04723 #if defined(RCC_PLLSAI1_SUPPORT) 04724 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 04725 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ 04726 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ 04727 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) 04728 #endif /* RCC_PLLSAI1_SUPPORT */ 04729 04730 #if defined(RCC_PLLSAI2_SUPPORT) 04731 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 04732 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 04733 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ 04734 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) 04735 #elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 04736 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 04737 (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ 04738 (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ 04739 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) 04740 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 04741 #endif /* RCC_PLLSAI2_SUPPORT */ 04742 04743 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 04744 ((__RANGE__) == RCC_MSIRANGE_1) || \ 04745 ((__RANGE__) == RCC_MSIRANGE_2) || \ 04746 ((__RANGE__) == RCC_MSIRANGE_3) || \ 04747 ((__RANGE__) == RCC_MSIRANGE_4) || \ 04748 ((__RANGE__) == RCC_MSIRANGE_5) || \ 04749 ((__RANGE__) == RCC_MSIRANGE_6) || \ 04750 ((__RANGE__) == RCC_MSIRANGE_7) || \ 04751 ((__RANGE__) == RCC_MSIRANGE_8) || \ 04752 ((__RANGE__) == RCC_MSIRANGE_9) || \ 04753 ((__RANGE__) == RCC_MSIRANGE_10) || \ 04754 ((__RANGE__) == RCC_MSIRANGE_11)) 04755 04756 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 04757 ((__RANGE__) == RCC_MSIRANGE_5) || \ 04758 ((__RANGE__) == RCC_MSIRANGE_6) || \ 04759 ((__RANGE__) == RCC_MSIRANGE_7)) 04760 04761 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) 04762 04763 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 04764 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 04765 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 04766 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 04767 04768 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 04769 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 04770 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 04771 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 04772 ((__HCLK__) == RCC_SYSCLK_DIV512)) 04773 04774 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 04775 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 04776 ((__PCLK__) == RCC_HCLK_DIV16)) 04777 04778 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 04779 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 04780 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 04781 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 04782 04783 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) 04784 04785 #if defined(RCC_HSI48_SUPPORT) 04786 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 04787 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 04788 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 04789 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 04790 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 04791 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 04792 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 04793 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 04794 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 04795 #else 04796 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 04797 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 04798 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 04799 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 04800 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 04801 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 04802 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 04803 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 04804 #endif /* RCC_HSI48_SUPPORT */ 04805 04806 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 04807 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 04808 ((__DIV__) == RCC_MCODIV_16)) 04809 04810 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 04811 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 04812 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 04813 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 04814 04815 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 04816 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 04817 /** 04818 * @} 04819 */ 04820 04821 /* Include RCC HAL Extended module */ 04822 #include "stm32l4xx_hal_rcc_ex.h" 04823 04824 /* Exported functions --------------------------------------------------------*/ 04825 /** @addtogroup RCC_Exported_Functions 04826 * @{ 04827 */ 04828 04829 04830 /** @addtogroup RCC_Exported_Functions_Group1 04831 * @{ 04832 */ 04833 04834 /* Initialization and de-initialization functions ******************************/ 04835 HAL_StatusTypeDef HAL_RCC_DeInit(void); 04836 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 04837 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 04838 04839 /** 04840 * @} 04841 */ 04842 04843 /** @addtogroup RCC_Exported_Functions_Group2 04844 * @{ 04845 */ 04846 04847 /* Peripheral Control functions ************************************************/ 04848 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 04849 void HAL_RCC_EnableCSS(void); 04850 uint32_t HAL_RCC_GetSysClockFreq(void); 04851 uint32_t HAL_RCC_GetHCLKFreq(void); 04852 uint32_t HAL_RCC_GetPCLK1Freq(void); 04853 uint32_t HAL_RCC_GetPCLK2Freq(void); 04854 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 04855 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 04856 /* CSS NMI IRQ handler */ 04857 void HAL_RCC_NMI_IRQHandler(void); 04858 /* User Callbacks in non blocking mode (IT mode) */ 04859 void HAL_RCC_CSSCallback(void); 04860 04861 uint32_t HAL_RCC_GetResetSource(void); 04862 /** 04863 * @} 04864 */ 04865 04866 /** 04867 * @} 04868 */ 04869 04870 /** 04871 * @} 04872 */ 04873 04874 /** 04875 * @} 04876 */ 04877 04878 #ifdef __cplusplus 04879 } 04880 #endif 04881 04882 #endif /* STM32L4xx_HAL_RCC_H */ 04883
1.7.6.1